Due to a problem in the Intel® Quartus® Prime Pro Edition 18.0 and earlier, you may see this internal error when implementing a LVDS SERDES IP with Use external PLL option where its LVDS external ports ext_loaden and ext_fclk connect directly to top level.
Device Family: Intel® Arria® 10, Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Last Modified: December 26, 2018
Version Found: v18.0
Bug ID: FB: 565494;