Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: October 10, 2018
Bug ID: FB: 590454;
IP: Altera S10 Mailbox Client Core

How can data be pre-stored into the write data FIFO in Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core with JTAG Master as Host?

Description

The write data FIFO is referring to the “wr_mem” bus in Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core. To pre-store data into write data FIFO, you need to write data to the “wr_mem” bus. You may refer to the IP wr_mem’s base and end address in the Intel® Quartus® Prime Platform Designer for the start address and list of addresses that you can write into. 

 

For more details about the write operation flow, you may refer to Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core User Guide.

 

Workaround/Fix