Device Family: Intel® Stratix® 10

Type: Answers

Area: Component


Last Modified: October 10, 2018
Bug ID: FB: 573347;

Error (175006): There is no routing connectivity between the IOPLL and destination LVDS_CHANNEL

Description

You may see this error in the Intel® Quartus® Prime Pro software when using LVDS SERDES Intel FPGA IP with Intel Stratix® 10 devices. This error is occurs when the input clock signal of the IOPLL is being sourced through the FPGA core

Workaround/Fix

To avoid this error, provide the input clock signal to the IOPLL through dedicated clock pins.