Device Family: Intel® Stratix® 10 MX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component, Tools


Last Modified: November 19, 2018
Version Found: v18.0 Update 1
Bug ID: FB: 597826;

Internal Error: Sub-system: FPP, File: /quartus/periph/fpp/fpp_design.cpp, Line: 213 Port OPORT_BUFFEROUT already exists on IO_CLUSTER cell 177

Description

You may see this error message when targeting Intel® Stratix® 10 MX devices in Intel® Quartus® Prime Pro software version 18.0.1 and you have a design that includes two instances of the eSRAM Intel® FPGA IP, and both of the instances share a common reference clock signal.

Each eSRAM Intel® FPGA IP instance requires a dedicated reference clock due to their physical placement on the device.

Workaround/Fix

To work around this problem, provide a dedicated reference clock to each of eSRAM Intel® IP instances in the design. Please refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines for more information related to the eSRAM Intel® IP pin requirements.

A more meaningful error message will be generated in a future release of the Intel® Quartus® Prime software.