Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component

Last Modified: June 08, 2018
Version Found: v18.0
Bug ID: FB: 528586;
IP: Altera IOPLL

Why does my downstream IOPLL fail to lock when cascading IOPLLs in Intel® Stratix® 10 devices?


When cascading IOPLLs in Intel® Stratix® 10 devices, if the downstream IOPLL has calibrated before the upstream IOPLL or if the upstream IOPLLs calibration has failed, this may cause cause the downstream IOPLL not to lock.



Connect  the permit_cal input of the downstream IOPLL to the locked output of the upstream IOPLL when cascading IOPLLs to prevent the downtream IOPLL calibrating before the upstream IOPLL has completed calibration and has locked to its incoming clock.