Device Family: Intel® Stratix® 10

Type: Answers

Area: Component


Last Modified: December 01, 2017
Version Found: v17.0
Version Fixed: v17.1
Bug ID: FB: 505476;
IP: Altera LVDS SERDES

Is the Clock Phase Alignment (CPA) block of the Altera LVDS IP supported for all SERDES factors in Stratix 10 devices?

Description

The Clock Phase Alignment (CPA) block of the Altera® LVDS IP in Intel® Stratix® 10 devices is supported for all SERDES factors from Quartus® Prime Pro version 17.1 onwards under the following conditions:

  • The Use external PLL option is turned off.
  • The IP core functional mode is TX, RX Non-DPA, or RX DPA-FIFO.
  • The tx_outclock phase shift is a multiple of 180°