Device Family: Intel® Stratix® 10 SX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Embedded, OpenCL, Programmable Acceleration Cards


Last Modified: November 08, 2019
Version Found: v18.1 Update 2
Bug ID: 1507312888

Why the "Compute Score" OpenCL™ example design hang  on the Intel® Programmable Acceleration Card D5005?

Description

If you run the OpenCL™ example design "compure_score" on the Intel® Programmable Acceleration Card D5005, you may find the example design hangs and does not produce results.  You may see something similar to the following:

[root@localhost bin]# ./host

RAND_MAX: 2147483647

Allocating and setting up data

Creating Documents total_terms=108157184 (no_pad=91552735)

Creating Profile

...

Setting up OpenCL

Platform: Intel(R) FPGA SDK for OpenCL(TM)

Using 1 device(s)

  pac_s10_dc : Intel PAC Platform (pac_ee00000)

Using AOCX: compute_score.aocx

Kernel Compilation Time: 0.016351 ms

..........................................hang in here and cannot get result..................................

 

This is because  partial reconfiguration (PR) compile using OpenCL™ may produce hold time violations in the static regions. You can find the “afu_default.failing_clocks.rpt/afu_default.failing_paths.rpt” files on the output folder.

Workaround/Fix

To work around this problem, you should recompile it using a different seed with the command: aoc <kernal_name.cl> -seed=<integer>. For example: aoc hello_world.cl -seed=5.

This problem is scheduled to be fixed in a future release of the Intel® Acceleration Stack for Intel Xeon® CPU with FPGAs.