PCI Express Reference Designs and Application Notes

Altera offers a host of PCI Express® (PCIe®) reference designs and application notes. These reference designs and application notes offer
ready-made solutions that can leveraged for feasibility studies, device selections, and design proofing on Altera® FPGAs and SoCs.

The Altera development kits complement the reference designs and application notes by delivering a complete system-level design environment that includes both the hardware and software needed to immediately begin developing designs. Each reference design indicates which Altera development kit and version of the Quartus® II software were used for its development cycle.

As PCIe is a very configurable intellectual property (IP) solution and supports numerous application needs, we cannot offer reference designs for every configuration or application possible. If there is no readily available reference design for your particular configuration or device, you may use a similar design and modify and/or port it as needed to fit your design requirements.

Table 1 describes the various reference designs and application notes available for PCIe applications.

Table 1. Reference Design and Application Note Support

Name Application Note/
Wiki/
Other
Development Kit Used Quartus II Software Version Design Flow Qsys/MW2/
Other
EP/RP1 AVST3/
AVMM4/
AVMM with DMA
User Interface/
PCIe Gen and Link Width/
Device Driver Operating System Support
PCIe WITH EXTERNAL MEMORY INTERFACE REFERENCE DESIGN
PCIe AVMM with Direct Memory Access (DMA) and DDR3 Memory Interface AN708 Stratix® V GX FPGA Development Kit 14.0 Qsys EP AVMM with DMA

256 bit: Gen3x8
Linux

PCIe WITH ON-CHIP MEMORY INTERFACE REFERENCE DESIGNS
PCIe AVMM with DMA and On-Chip Memory Interface AN690 Stratix V GX FPGA Development Kit 14.0 Qsys EP AVMM with DMA

256 bit: Gen3x8
Linux

PCIe AVMM with DMA and On-Chip Memory Interface FPGA Wiki Arria® V GT FPGA Development Kit Pre-14.0 release5  Qsys EP AVMM with DMA

128 bit: Gen2x4
Linux

 
PCIe AVMM with DMA and On-Chip Memory Interface Arria V GX Starter Kit
PCIe AVMM with DMA and On-Chip Memory Interface FPGA Wiki Cyclone® V GT FPGA Development Kit
PCIe AVMM with DMA and On-Chip Memory Interface (Linux Driver) FPGA Wiki (AV)
FPGA Wiki (CV)
 
PCIe WITH SINGLE-ROOT I/O VIRTUALIZATION (SR-IOV) REFERENCE DESIGN
PCIe AVMM with DMA and SR-IOV Interface FPGA Wiki Stratix V GX FPGA Development Kit 14.0 Qsys EP AMM with DMA 256 bit: Gen3x8
PCIe WITH ON-CHIP MEMORY INTERFACE REFERENCE DESIGNS
PCIe AVST and On-Chip Memory Interface AN456 Stratix V GX FPGA Development Kit 14.0 Qsys EP Avalon-ST 64 bit: Gen1x1,
Gen1x4, Gen2x1,
Gen3x1
128 bit: Gen1x8,
Gen2x4, Gen2x8,
Gen3x4
Windows (Jungo Driver)
PCIe AVST and On-Chip Memory Interface Arria V GT FPGA Development Kit 64 bit: Gen1x1,
Gen1x4, Gen2x1
128 bit: Gen1x8, Genx2x4
Windows (Jungo Driver)
PCIe AVST and On-Chip Memory Interface Cyclone V GT FPGA Development Kit 64 bit: Gen1x1,
Gen1x4, Gen2x1
128 bit: Gen2x4
Windows (Jungo Driver)
PCIe AVST and On-Chip Memory Interface Stratix IV GX FPGA Development Kit 64 bit: Gen1x1,
Gen1x4, Gen2x1,
Gen2x4
128 bit: Gen1x8,
Gen2x4, Gen2x8
Windows (Jungo Driver)
PCIe AVST and On-Chip Memory Interface Cyclone IV GX FPGA Development Kit Hardened Protocol Stack IP Use
64 bit: Gen1x1,
Gen1x4
Soft Protocol Stack IP Use
64 bit: Gen1x1
Windows (Jungo Driver)
PCIe AVST and On-Chip Memory Interface Arria II GX FPGA Development Kit Hardened Protocol Stack IP Use
64 bit: Gen1x1, Gen1x4, Gen1x8
Soft Protocol Stack IP Use
64 bit: Gen1x1, Gen1x4
Windows (Jungo Driver)
PCIe WITH EXTERNAL MEMORY INTERFACE REFERENCE DESIGNS (Legacy Reference Designs)
PCIe AVST / AVMM and DDR2 / DDR3 Memory Interface AN431 Stratix IV GX FPGA Development Kit 11.0 SP1 Qsys EP AVST / AVMM 64 bit: Gen2x4
Windows (Jungo Driver)
Arria II GX FPGA Development Kit Hardened Protocol Stack IP Use
64 bit: Gen1x4
Windows (Jungo Driver)
OTHER PCIe COLLATERAL ITEMS AND TOOLS
MSI-X Implementation Guidelines for Altera FPGAs FPGA Wiki All 14.0 N/A EP AVST / AVMM N/A
Transceiver Toolkit for hardened PCIe IP (Gen1x8) FPGA Wiki Stratix V GX FPGA Development Kit 13.1 Qsys EP AVST 128 bit: Gen1x8, Gen2x8
256 bit: Gen3x8
Transceiver Toolkit for hardened PCIe IP (Gen2x8)
Transceiver Toolkit for hardened PCIe IP (Gen3x8)
  1. EP = Endpoint, RP = Root Port
  2. MW = MegaWizardTM 
  3. AVST = Avalon Streaming (Avalon-ST)
  4. AVMM = Avalon Memory-Mapped (Avalon-MM)
  5. Actual project is generated and compiled in Quartus II software v14.0 (internally released build) and is moved to Quartus II software v13.1 (public release). This enables customers to use designs while Altera completes the formal documentation release process of the upcoming Quartus II software publically released version.

Figure 1. Typical PCIe Application