This update can only be used with MAX+PLUS II version 9.01 or 9.02 for PCs or UNIX workstations. Do not use this update with any other version.
You should download and install this update (MAX+PLUS II version 9.03) if you wish to add the following support to MAX+PLUS II version 9.01 or 9.02.
Programming and compilation support for EPM7064AE devices in 44-pin plastic J-lead chip carrier (PLCC), 44-pin thin quad flat pack (TQFP), and 100-pin TQFP packages
Programming and compilation support for EPF10K50E devices in 144-pin, 208-pin, and 240-pin plastic quad flat pack (PQFP) packages
Corrected synthesis of MAX+PLUS II VHDL designs for the following operations:
Compare operations (>, >=, =, <, <=) on signals or ports of type SIGNED
Compare operations on integers that have negative values
MAX+PLUS II versions 9.01 and 9.02 treat these operations as UNSIGNED. This synthesis problem only impacts MAX+PLUS II VHDL designs. Third-party synthesis software tools (e.g., Exemplar Logic, Synopsys, and Synplicity) are not affected.
Corrected synthesis of VHDL designs when a bit or slice of a vector is assigned in a conditional statement and all branches of the conditional statement are not fully specified
Corrected synthesis of Verilog HDL designs when using concatenation inside Case Statements
If you have a question or problem that is not answered by the information provided here or in MAX+PLUS® II. Help, please inquire in the mySupport web site.