Schematic Symbols Cadence Capture CIS and Allegro DE-HDL Concept Software
- Tables below show the Cadence* Capture CIS schematic symbol for Intel® FPGA and CPLD device families.
Instructions to download the schematic symbol files:
- Right click on the .zip or .olb file name
- Select the option to Save link as...
- A window will pop-up to save the file in a location on your local computer
- Select the location where you would like to save the file and then click Save to download the file