IEEE 1532 BSDL Files

You can browse boundary-scan description language (BSDL) files by Intel® FPGA device family. You can use these BSDL files for pre-configuration boundary-scan test (BST). For post-configuration BSDL files, please refer to the Intel BSDL Support page. You can use the same BSDL file regardless of speed grade or temperature.

You will need an IEEE 1532 BSDL file (programming algorithm) and an in-system configurable (ISC) file (programming data) to execute in-system programmability (ISP). Methods of generating the ISC file can be obtained from the Intel Quartus® Prime Handbook.

 

Table 1. IEEE 1532-Compliant BSDL Files

Device Type Device Family Part Number Prefix
Configuration Devices Enhanced Configuration Device EPC
CPLDs
MAX® V 5M
  MAX® II EPM
  MAX 3000 EPM3
  MAX 7000 EPM7
FPGAs Intel MAX 10 10M

Table 2. IEEE 1532-Compliant Tools

Tool/Guideline FPGA CPLD Configuration Devices
svf2isc - - EPC
SVF to ISC Intel MAX 10 - -
SVF2ISC - MAX V -

If you have any questions or concerns about the contents of these files, visit Intel Premier Support.