The Quartus® Prime software incremental compilation feature is the most productive incremental design methodology for high-density FPGAs. It reduces compilation times by up to 70 percent while preserving the results of unchanged logic in your design.
To search for known incremental compilation issues and technical support solutions, use Altera’s Knowledge Database. You can also visit the Altera® Forum to discuss technical issues with other Altera users.
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Incremental compilation resources
Table 1 provides links to available documentation on incremental compilation.
This handbook chapter discusses important FPGA design planning issues, provides recommendations, and describes various tools available for use with Altera FPGAs to help you improve design productivity. It briefly describes how planning can improve your success with incremental compilation.
This handbook chapter describes Quartus Prime software features and design methodologies for incremental compilation, and includes various recommended design flows and application examples to help you meet your design goals. This is the primary document for details about incremental compilation.
This handbook chapter provides a set of guidelines to help you partition your design to take advantage of Quartus Prime incremental compilation, and to help you create a design floorplan (using Logic Lock Region) to support the flow.
Table 2 provides links to available training and demonstrations on incremental compilation.
Table 2. Incremental Compilation Training and Demonstrations
You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature. By the end of this training, you will be able to use Logic Lock Region in physical partitioning of your design. You will be able to segment your design into logical design partitions. You will be able to apply the incremental compilation methodology to both the top-down and bottom-up design flows.
You will learn advanced features of the Quartus II software that enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and Logic Lock Region in the Quartus II software to reduce compilation times and preserve performance.