Altera provides simulation libraries for both pre-routing functional simulation and post-routing timing simulation.
Pre-Routing Functional Simulation Libraries (VITAL-Compliant)
The /usr/maxplus2/synopsys/library/alt_pre/vital/src directory contains Altera® -provided VHDL simulation models in VITAL 95 format. This library contains functional descriptions of all primitives that appear in Altera-specific technology libraries. These libraries allow you to perform a functional or pre-routing simulation that verifies the netlist structure generated by the Synopsys Design Compiler or FPGA Compiler software. Altera provides the flex.cmp and flex.vhd files in the /usr/maxplus2/synopsys/library/alt_pre/vital/src directory.
Similarly, the /usr/maxplus2/synopsys/library/alt_pre/verilog/src directory contains Altera-provided Verilog HDL simulation models for all device families. The altera.v file can be used for simulation with the Cadence Verilog-XL simulator.
Pre-Routing Functional Simulation Libraries with Estimated Timing Information
The /usr/maxplus2/synopsys/library/alt_pre/<device family>/src directory contains Altera® -provided VHDL simulation libraries, which give both functional and area descriptions of all primitives that appear in all Altera technology libraries. These simulation libraries allow you to verify the function of VHDL projects, with estimated timing, after synthesizing them with the Synopsys Design Compiler or FPGA Compiler, but before submitting them to MAX+PLUS® II software for compilation.
Altera provides an encrypted Full Timing Structural Model (FTSM) and a Full Timing Gate-Level Simulation model (FTGS) for the VHDL simulation libraries listed in Table 1.