User Guides / Device Overview / Device Datasheet Published Date
Stratix® 10 GX/SX Device Overview 
2017-10-30
Intel® Stratix 10 Device Datasheet 2017-08-04
Intel Stratix 10 GX, MX, and SX Device Family Pin Connection Guidelines 2017-07-14
Intel Stratix 10 Clocking and PLL User Guide 2017-05-26
Intel Stratix 10 Configuration User Guide 2017-11-09
Intel Stratix 10 General Purpose I/O User Guide 2017-11-06
Intel Stratix 10 High-Speed LVDS I/O User Guide 2017-11-06
Intel Stratix 10 JTAG Boundary-Scan Testing User Guide 2017-11-06
Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide 2017-11-06
Intel Stratix 10 Power Management User Guide 2017-05-08
Intel Stratix 10 SEU Mitigation User Guide 2016-12-09
Intel Stratix 10 Analog to Digital Converter User Guide 2017-11-06
Intel Stratix 10 Device Design Guidelines 2017-02-13
Intel Stratix 10 Embedded Memory User Guide 2017-11-06
Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide 2017-08-11
Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide 2017-08-11
Intel Stratix 10 MX (DRAM System-in-Package) Device Overview 2017-10-30
Mailbox Client Intel Stratix 10 FPGA IP Core User Guide 2018-02-14
Application Notes Published Date
Power Sequencing Considerations for Intel Cyclone® 10 GX, Intel Arria® 10 and Intel Stratix 10 Devices 2017-05-08
Designing for Stratix 10 Devices with Power in Mind 2016-06-14
Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline 2017-05-08
Intel Stratix 10 Transceiver Usage 2017-11-06
 Title Published Date
  Configuration for Stratix® 10 Devices OCNFGS10
  Stratix 10 Transceiver Basics OSEUHIER
 Title Published Date
  Arria® 10 and Stratix® 10 EMIF Hardware Debug Guide 2017-03-11

External Memory Interface

Ethernet

PCI Express*

Other Serial IP

Transceiver PHY

Digital Signal Processing (DSP)

Embedded

User Guides Published Date
Intel® FPGA SDI II IP Core User Guide 2017-11-06

Audio and Video

User Guides Published Date
Embedded Peripherals IP User Guide 2017-11-06

Ethernet

PCI Express*

Other Serial IP

Title Published Date
Intel® FPGA IP Release Notes 2017-11-30

External Memory Interface

Other Serial IP

Title Published Date
Altera® JESD204B IP Quick Start Video 2016-05-03

External Memory Interface

PCI Express*

Title Published Date
 Reference Design: Gen3x8 AVMM DMA - Stratix® 10  2017-04-14

The Intel® Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Handbook.

The Intel® Quartus® Prime design software also comes with Intel® High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for Intel® FPGA products

Title Published Date
Timing Analyzer Design Examples 2010-01-01
User Guides / Device Overview / Device Datasheet Published Date
Programmer User Guide: Intel Quartus Prime Pro Edition 2018-06-27
Analyzing and Debugging Designs with System Console 2018-07-03
Design Debugging Using In-System Sources and Probes 2018-07-03
Debug Tools User Guide: Intel Quartus Prime Pro Edition 2018-07-03
Altera® Virtual JTAG (altera_virtual_jtag) IP Core User Guide 2016-10-31
Analyzing and Debugging Designs with System Console 2018-07-03
FPGA-Adaptive Software Debug and Performance Analysis  --
System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug  --
ByteBlaster II Download Cable User Guide  --
Intel FPGA USB Download Cable User Guide 2016-10-31
Intel FPGA Download Cable II User Guide  2018-04-19
EthernetBlaster Communications Cable User Guide 2016-10-28
BSDL Support  --
Application Notes Published Date
AN 827: Unified Tool for Generating Programming Files 2018-05-07
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder SystemsDesign files  --
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer  --
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile 2017-05-08
AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC 2015-05-11
AN 541: SerialLite II Hardware Debugging Guide  --
AN 543: Debugging Nios II Software Using the Lauterbach Debugger  --
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench  --
AN 624: Debugging with System Console over TCP/IP  --

Still Have Questions?

If you are unable to find something on this page, go though a list of knowledge base articles published on the Knowledge Base Center or raise a service request using Intel Premier Support.

Explore Other Developer Centers

For other design guidelines, visit the following Developer Centers:

  • Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Intel® FPGAs and SoC FPGAs
  • Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs
  • System Architect Developer Center - Contains information on how Intel® FPGAs can add value to your system design 

Click on the following links below to explore other Developer Centers now.