User Guides / Device Overview / Device Datasheet Published Date
Intel® MAX® 10 FPGA Device Datasheet 2017-12-15
Intel MAX 10 Clocking and PLL User Guide 2017-12-29
Intel MAX 10 Analog to Digital Converter User Guide 2017-12-15
Intel MAX 10 FPGA Device Overview 2017-12-15
Intel MAX 10 General Purpose I/O User Guide 2017-12-15
Intel MAX 10 High-Speed LVDS I/O User Guide 2017-12-15
Intel MAX 10 FPGA Configuration User Guide 2018-02-12
Intel MAX 10 Power Management User Guide 2017-05-26
MAX 10 Embedded Memory User Guide 2017-02-21
MAX 10 FPGA Device Architecture 2017-02-21
MAX 10 JTAG Boundary-Scan Testing User Guide 2017-02-21
MAX 10 User Flash Memory User Guide 2017-02-21
Intel MAX 10 FPGA Signal Integrity Design Guidelines 2017-12-15
Intel MAX 10 FPGA Device Family Pin Connection Guidelines 2017-12-15
Intel MAX 10 FPGA Design Guidelines 2017-05-03
Intel MAX 10 FPGA Schematic Review Worksheet 2017-06-01
Intel FPGA Parallel Flash Loader IP Core User Guide 2017-11-06
Altera® Remote Update IP Core User Guide 2017-04-10
  Application Notes Published Date
AN 286: Implementing LED Drivers in Altera MAX Series 2017-12-13
AN 773: Drive-On-Chip Reference Design for MAX 10 Devices 2017-11-24
AN 100: In-System Programmability Guidelines 2014-09-22
AN 265: Using Altera MAX Series as Microcontroller I/O Expanders 2014-09-22
AN 294: Crosspoint Switch Matrices in Altera MAX Series 2014-09-22
AN 425: Using the Command-Line Jam™ STAPL Solution for Device Programming 2014-09-22
AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems 2017-11-06
AN 486: SPI to I2C Using Altera MAX Series 2014-09-22
AN 488: Stepper Motor Controller Using Altera MAX Series 2014-09-22
AN 490: Altera MAX Series as Voltage Level Shifters 2014-09-22
AN 491: Power Sequence Auto Start Using Altera MAX Series 2014-09-22
AN 492: CF+ Interface Using Altera MAX Series 2014-09-22
AN 493: I2C Battery Gauge Interface Using Altera MAX Series 2014-09-22
AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series 2014-09-22
AN 495: IDE/ATA Controller Using Altera MAX Series 2014-09-22
AN 496: Using the Internal Oscillator IP Core 2017-11-06
AN 498: LED Blink Using Power Sequencing in Altera MAX Series 2014-09-22
AN 500: NAND Flash Memory Interface with Altera MAX Series 2014-09-22
AN 501: Pulse Width Modulation Using Altera MAX Series 2014-09-22
AN 502: Implementing SMBus Controller in Altera MAX Series --
AN 509: Multiplexing SDIO Devices Using Altera MAX Series 2014-09-22
AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families 2017-11-06
AN 630: Real-Time ISP and ISP Clamp for Altera MAX Series 2014-09-22
AN 631: Replacing Serial EEPROMs with User Flash Memory in Altera MAX Series 2014-09-22
AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios®II Processor 2017-02-21
AN 752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP) 2015-11-02
AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus® Prime Software 2017-12-18
Title Published Date
MAX® 10 I2C to RSU 2015-08-16
MAX® 10 On-Chip Flash IP Read Operation Example 2017-11-09
Title Published Date
Altera® Jam™ STAPL Software --

External Memory Interface

User Guides / Device Overview / Device Datasheet Published Date
MAX® 10 External Memory Interface User Guide 2017-02-21
External Memory Interface Handbook 2017-05-08

Ethernet

DSP

Embedded

User Guides Published Date
Embedded Peripherals IP User Guide 2017-11-06
Title Published Date
Intel® FPGA IP Release Notes 2017-11-30
User Guides / Device Overview / Device Datasheet Published Date
Platform Designer User Guide 2018-05-07
DSP Builder for Intel® FPGAs --
MAX® 10 FPGA Design Guidelines 2014-09-22
Title Published Date
Altera® EMIF Resources and Pin Planning Tool 2015-02-24

The Intel® Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Handbook.

User Guides / Device Overview / Device Datasheet Published Date
Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis 2018-05-09
Advanced Synthesis Cookbook 2011-07-01
White Paper Reference ID
Applying the Benefits of Network on a Chip Architecture to FPGA System Design WP-01149-1.2 
Title Published Date
Timing Analyzer Design Examples 2010-01-01

Still Have Questions?

If you are unable to find something on this page, go though a list of knowledge base articles that are published on the Knowledge Base Center or raise a service request using Intel Premier Support.

Explore Other Developer Centers

For other design guidelines, visit the following Developer Centers:

  • Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Intel® FPGAs and SoC FPGAs
  • Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs
  • System Architect Developer Center - Contains information on how Intel® FPGAs can add value to your system design 

Click on the following links below to explore other Developer Centers now.