Documentation
User Guides / Device Overview / Device Datasheet Published Date
Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook 2017-12-15
Intel Arria 10 Device Datasheet 2018-01-09
Intel Arria 10 Device Overview 2018-01-17
Intel Arria 10 GX/GT Device Errata and Design Recommendations 2017-12-20
Intel Arria 10 Transceiver PHY User Guide 2017-11-06
Power Sequencing Considerations for Intel Cyclone® 10 GX, Intel Arria 10, and Intel Stratix® 10 Devices 2017-05-08
Altera® I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide 2017-06-16
Intel FPGA Chip ID IP Cores User Guide 2017-12-11
Intel Arria 10 External Memory Interfaces IP User Guide 2017-11-06
Intel Arria 10 External Memory Interfaces IP Design Example User Guide 2017-11-06
Intel Arria 10 External Memory Interface IP Core Release Notes 2017-05-08
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide 2017-12-15
Intel FPGA Voltage Sensor IP Core User Guide 2018-02-09
Early Power Estimator for Intel Arria 10 FPGAs User Guide 2016-11-07
Intel FPGA Temperature Sensor IP Core User Guide 2017-09-14
Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines 2017-06-16
Intel FPGA Parallel Flash Loader IP Core User Guide 2017-11-06
Altera ASMI Parallel II IP Core User Guide 2017-05-08
Altera ASMI Parallel IP Core User Guide 2017-05-31
Altera Remote Update IP Core User Guide 2017-04-10
Application Notes Published Date
AN 556: Using the Design Security Features in Intel FPGAs 2017-12-18
AN 496: Using the Internal Oscillator IP Core 2017-11-06
AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families 2017-11-06
AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines 2017-05-08
AN 711: Power Reduction Features in Intel Arria 10 Devices 2017-05-08
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 Devices 2016-05-05
AN 737: SEU Detection and Recovery in Intel Arria 10 Devices 2017-03-15
AN 738: Intel Arria 10 Device Design Guidelines 2017-06-30
AN 742: PMBus SmartVID Controller Reference Designs 2017-05-08
AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus® Prime Software 2017-12-18
Design Examples
Title Published Date
Arria® 10 Internal Temperature Sensor Reference Design  2016-01-13
Arria 10 IOPLL Multiple Profile Reconfiguration  2017-12-13
Known Issues
Training and Videos
Title Course ID
Mitigating Single Event Upsets in Arria® 10 Devices OSEUMTGTN
SEU Mitigation in Intel® FPGA Devices: Hierarchy Tagging OSEUHIER
Partial Reconfiguration for Intel Arria 10 Devices: Design Guidelines & Host Requirements OPR201
Partial Reconfiguration for Intel Arria 10 Devices: Introduction & Project Assignments OPR200
Partial Reconfiguration for Intel Arria 10 Devices: Output Files & Demonstration OPR203
Partial Reconfiguration for Intel Arria 10 Devices: PR IP Core & Project Flow OPR202
Partial Reconfiguration with Arria 10 FPGAs IPR200
Advanced Signal Conditioning for Arria 10 FPGA Transceivers OADVSIGA10
Building a Generation 10 Transceiver PHY Layer OG10XCVRPHY
Building Gigabit Interfaces in 28-nm Devices ITRNSCVR
Building Interfaces with Arria 10 High-Speed Transceivers ITRNSCVRGEN10
Generation 10 Transceiver Clocking OG10XCVRCLK
Transceiver Basics for 20 nm and 28 nm Devices OSIIGX1115
Intel Arria 10 Device Videos --
Development Kits
Title
Arria® 10 GX FPGA Development Kit
Arria 10 GX Transceiver Signal Integrity Development Kit
Intel Arria 10 SoC Development Kit
Intel® Programmable Acceleration Card with Intel Arria 10 GX FPGA
Intel FPGA Wiki
Title  Published Date
Arria® 10 LVDS Basic Design Examples 2017-03-15
Arria 10 Voltage Sensor 2014-12-16
Documentation

External Memory Interface

User Guides Published Date
Intel® Arria® 10 External Memory Interfaces IP User Guide 2017-11-06
Intel Arria 10 External Memory Interfaces IP Design Example User Guide 2017-11-06
Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide 2017-11-30

Ethernet

User Guides Published Date
Intel® FPGA Triple-Speed Ethernet IP Core User Guide 2017-11-06
Intel FPGA Low Latency Ethernet 10G MAC User Guide 2017-12-25
Intel Arria® 10 25 Gbps Ethernet IP Core User Guide 2017-11-07
50 Gbps Ethernet IP Core User Guide 2017-11-07
Low Latency 100-Gbps Ethernet IP Core User Guide 2018-01-03
Low Latency 40-Gbps Ethernet IP Core User Guide 2018-01-03
Intel Arria 10 Transceiver PHY User Guide 2017-11-06
Application Notes Published Date
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench 2009-08-01
AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design 2015-12-14
AN 735: Altera® Low Latency Ethernet 10G MAC IP Core Migration Guidelines 2015-05-04
AN 808: Migration Guidelines from Arria 10 to Stratix® 10 for 10G Ethernet Subsystem 2017-06-19
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria 10 Devices 2017-02-01
AN 699: Using the Altera Ethernet Design Toolkit 2016-05-13
AN 701: Scalable Low Latency Ethernet 10G MAC Using Intel Arria 10 1G/10G PHY 2017-11-06
AN 794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design 2017-02-01
AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices 2016-05-13

PCI Express*

User Guides Published Date
Arria® 10 Hard IP for PCI Express* IP Cores 2015-08-26
Intel® Arria 10 and Intel Cyclone® 10 Avalon® -ST Interface for PCIe* User Guide 2017-10-14
Intel Arria 10 or Intel Cyclone 10 Avalon -MM DMA Interface for PCIe Solutions User Guide 2017-11-06
Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe User Guide 2017-11-06
Intel Arria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide 2017-12-12
Arria 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide 2016-10-21
Application Notes Published Date 
PCI Express: Migrating to Stratix® 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces 2017-01-23
PCI Express DMA Reference Design Using External Memory 2017-05-17
PCI Express High Performance Reference Design 2017-04-20
PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces 2017-01-23

Other Serial IP

User Guides Published Date
JESD204B IP Core User Guide 2017-11-06
RapidIO* II IP Core User Guide 2017-12-18
Application Notes Published Date
AN 753: Altera® JESD204B IP Core and ADI AD6676 Hardware Checkout Report 2015-11-02
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report 2015-12-18
AN 809: SerialLite III IP Core Feature and Interface Differences Between Stratix® 10, Arria® 10, and Stratix V 2017-06-19
Interlaken IP Core Feature and Interface Differences Between Stratix 10, Arria 10, and Stratix V Devices 2017-06-12

Digital Signal Processing (DSP)

User Guides Published Date
LDPC IP Core User Guide 2017-11-06
ALTERA_CORDIC IP Core User Guide 2017-05-08
BCH IP Core USer Guide 2017-01-06
FFT IP Core User Guide 2016-05-01
FIR II IP Core User Guide 2016-05-01
Viterbi IP Core User Guide 2017-11-06
Turbo IP Core User Guide 2015-11-11
Floating-Point IP Cores User Guide 2016-12-09
High-Speed Reed-Solomon IP Core User Guide 2017-11-06
Reed-Solomon II IP Core User Guide 2016-05-02
NCO IP Core User Guide 2017-11-06
Random Number Generator IP Core User Guide 2017-02-21

Embedded

User Guides Published Date
Embedded Peripherals IP User Guide 2017-11-06

Audio and Video

User Guides Published Date
Intel® FPGA SDI II IP Core User Guide 2017-11-06
Design Examples

External Memory Interface

Title Version
Arria® 10 DDR3 x40 with EMIF Debug Toolkit 15.0

Ethernet

Title Published Date
25G Ethernet Design Example User Guide 2017-11-08
50G Ethernet Design Example User Guide 2017-11-08
Low Latency 100G Ethernet Design Example User Guide 2017-11-08
Low Latency 40G Ethernet Example Design User Guide 2017-11-08
Intel® FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria® 10 Devices 2017-11-13

PCI Express*

Title Published Date
Intel® Arria® 10 and Intel Cyclone® 10 Avalon®-ST Hard IP for PCIe* Design Example User Guide 2017-11-06
Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe Design Example User Guide 2017-11-06

Other Serial IP

Title Published Date
JESD204B IP Core Design Example User Guide 2017-11-06
Intel® FPGA JESD204B Design Example User Guide for Intel Arria® 10 Devices 2017-11-06
Known Issues
Title Published Date
Intel® FPGA IP Release Notes 2017-11-30
Training and Videos

External Memory Interface

Title Course ID
Guide for New External Memory Interface (EMIF) Spec Estimator --
External Memory Interface Device Selector Tutorial --
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2 --
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2 --
DDR4 Ping Pong PHY --
How to Generate Arria® 10 EMIF Example Design --
Creating Multiple Arria 10 Memory Designs with Qsys --
Simulating an Arria 10 External Memory Interface --
Arria 10 FPGA & SoC EMIF --
How to Implement Package Deskew in External Memory Interface Design in Stratix® 10 and Arria 10 --
Board Timing for Arria 10 EMIF IP --
Implementing Over Constraint in Arria 10 External Memory Interface --
Automated Check of Altera® External Memory Interfaces Board Layout Guidelines --
Arria 10 External Memory Interface Toolkit --
Arria 10 EMIF Example Traffic Generator --
Using the Soft Nios® Processor to Debug Arria 10 External Memory Interfaces --
Arria 10 External Memory Interface Read and Write 2-D Eye Diagram --
External Memory Interface Driver Margining Part 1 --
External Memory Interface Driver Margining Part 2 --
How to Build RLDRAM3 EMIF Design for Arria 10 Development Kit and Test the Calibration Status Using EMIF Toolkit --
Altera® PHYLite Demo Part 1 --
Altera PHYLite Demo Part 2 --
Building Parallel Interfaces with Altera PHYLite IP --
How to Perform Group Pin Placement for PHYLite IP --
Generating PHYLite Example Design Simulation in ModelSim* in 16.1 with Arria 10 --
How to Create the OCT Block for Calibrated Termination I/O Buffer in Altera PHYLIte IP --
How to Estimate Arria 10 / Stratix 10 PHYLite Input and Output Path Latency --
How to Configure A10 /S10 Altera PHYLite Input and Output Delay Constraints --
How to Configure PHYLite IP Dynamic Reconfiguration Timing Settings --
Introduction to Memory Interfaces IP in Arria 10 & Stratix 10 Devices  0MEM1121
Integrating Memory Interfaces IP in Arria 10 Devices  0MEM1122
Verifying Memory Interfaces IP in Arria 10 Devices 0MEM1123
On-Chip Debugging of Memory Interfaces IP in Arria 10 Devices  0MEM1124

PCI Express*

Title Published Date
PCIe* Avalon® Memory Master DMA Reference Design in Arria® 10 Part1 2016-09-18
PCIe Avalon Memory Master DMA Reference Design in Arria 10 Part2 2016-09-18

Other Serial IP

Title Published Date
Altera® JESD204B IP Quick Start Video 2016-05-03
Intel FPGA Wiki

External Memory Interface

Title Published Date
EMIF Device Selector 2017-08-03
Arria® 10 Multiple EMIF Example Designs in Qsys 2015-11-06
Board Skew Parameter Tool Guide 2017-11-15
Arria 10 EMIF Simulation Guidance 2016-10-12
Generating and Modifying IBIS files for Arria 10 EMIF 2016-01-21
Calculating Channel Loss from DDRx Batch Wizard Results 2017-08-02
Automated EMIF Layout Checks 2015-06-30
Arria 10 and Stratix® 10 EMIF Hardware Debug Guide 2017-03-22
Arria 10 Debugging Multiple EMIFs 2016-04-20
Arria 10 EMIF Debug GUI 2016-11-29
Documentation
User Guides / Device Overview / Device Datasheet Published Date
Getting Started User Guide: Intel Quartus Prime Pro Edition  2018-05-07
Platform Designer User Guide (Intel® Quartus® Prime Pro Edition) 2018-05-07
DSP Builder for Intel® FPGAs --
Application Notes Published Date
AN 738: Intel Arria® 10 Device Design Guidelines 2017-06-30
AN 763: Arria 10 SoC Device Design Guidelines 2017-05-08
Design Examples
Title Published Date
BluePrint Reference Design Part 1 --
BluePrint Reference Design Part 2 --
Training and Videos
Title Course ID
Fast & Easy I/O System Design with BluePrint --
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2 --
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2 --
Altera® EMIF Resource and Pin Planning (AERP) Tool --
Manage Device I/Os with the Pin Planner Tool in the Quartus® II Software --
Intel FPGA Wiki
Title Published Date
Altera® EMIF Resources and Pin Planning Tool --
Arria® 10 Transceiver PHY Pin Planning --
Documentation

The Intel® Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these template, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Edition Handbook.

The Intel® Quartus® Prime design software also comes with Intel® High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for Intel® FPGA products.

User Guides / Device Overview / Device Datasheet Published Date
Design Recommendations User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Intel High Level Synthesis Compiler Getting Started Guide 2018-05-07
Intel High Level Synthesis Compiler User Guide 2018-05-07
Platform Designer User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Scripting User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Advanced Synthesis Cookbook 2011-07-01
Intel High Level Synthesis Compiler Best Practices Guide 2018-05-07
Intel High Level Synthesis Compiler Reference Manual 2018-05-07
Intel High Level Synthesis Compiler Release Notes 2018-05-07
Advanced Synthesis Cookbook 2011-07-01
White Paper Reference ID
Applying the Benefits of Network on a Chip Architecture to FPGA System Design WP-01149-1.2 
Design Examples
Title Published Date
Platform Designer Design Examples --
Platform Designer Pro Tutorial Design Example for Intel® Arria® 10 FPGA (.zip) --
Platform Designer Tutorial Design Example for Intel Arria 10 FPGA (.zip) --
Platform Designer Tutorial Design Example (.zip) --
VHDL Examples  --
Verilog Examples --
Intel Quartus® Design Examples --
Training and Videos
Title Published Date
Using the Quartus® Prime Software: An Introduction ODSW1100
Introduction to Verilog HDL IHDL120
Verilog HDL Basics OHDL1120
Advanced Verilog HDL Design Techniques IHDL230
SystemVerilog with the Quartus II Software OHDL1125
Introduction to VHDL IHDL110
VHDL Basics OHDL1110
Advanced VHDL Design Techniques IHDL240
Introduction to Platform Designer OQSYS1000
Platform Designer in the Intel® Quartus Prime Pro Edition Software OQSYSPRO
Creating a System Design with Platform Designer: Getting Started OQSYSCREATE
Using Spectra-Q Synthesis in the Quartus Prime Software OSYNQPRO
Good High-Speed Design Practices ODSWTC01
Software Downloads
Title Published Date
Download center for all versions of the Intel® Quartus® Prime software 2017-11-06
Documentation
User Guides / Device Overview / Device Datasheet Published Date
Intel® Quartus® Prime Standard Edition Handbook Volume 3: Verification 2017-11-06
Third-party Simulation User Guide (Intel Quartus Prime Pro Edition)  2018-05-07
Simulation Quick-Start for ModelSim*-Intel® FPGA Edition  2017-07-15
Avalon® Verification IP Suite User Guide  2016-12-13
Mentor Verification IP Altera Edition AMBA* AXI3 and AXI4 User Guide  --
Intel FPGA Software Installation and Licensing   2017-11-06
ModelSim - Leading Simulation and and Debugging    --
Simulating the a8251 Model with the Visual IP Software  --
Simulating the a8259 Model with the Visual IP Software  --
Simulating the Reed-Solomon Model with the Visual IP Software  --
Simulating the Turbo Encoder/Decoder Model with the Visual IP Software  --
Application Notes Published Date
AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Intel Stratix®10 Devices 2017-05-30
AN 720: Simulating the ASMI Block in Your Design 2015-08-03
AN 351: Simulating Nios®II Processor Designs 2017-11-06
AN 508: Cyclone® III Simultaneous Switching Noise (SSN) Design Guidelines --
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench --
Simulating Altera® Devices with IBIS Models --
Simulating Intel FPGA Designs --
Design Examples
Title Published Date
Avalon® Verification IP Suite Design Example --
Avalon Verification IP Suite Design Example on Arria® 10   --
Triple Rate SDI II Quad Instance Simulation/Compilation Design Example    2016-09-16
Simulating the ASMI Block in Your Design for Arria 10 Device   --
Known Issues
Training and Videos
Title Course ID
Advanced System Design Using Qsys: System Verification with System Console AQSYSSYSCON
Advanced System Design Using Qsys: Component & System Simulation OAQSYSSIM
Design Software Online Demonstration --
Avalon® Verification Suite OAVL1100
Verifying Memory Interfaces IP in Arria® 10 Devices OMEM1123
Overview of Mentor Graphic's ModelSim* Software ODSW1120
Generating a Testbench with the Altera-ModelSim Simulation Tool --
Simulation of SoC HPS DDR3 Core --
How to Set Up RTL Simulations in Quartus, Qsys and Third Party Simulators --
Ping Pong PHY DDR3 Simulation --
Intel FPGA Wiki
Title Published Date
Simulating Designs with Lower-Level Qsys Systems --
Arria® 10 EMIF Simulation Guidance 2016-10-12
DDR4 Simulation Guidelines 2015-11-04
Simpler Chaining DMA Testbench Example --
Software Downloads
Title
Intel® FPGA Development Tools
Intel Quartus® Prime Software
Documentation
User Guides / Device Overview / Device Datasheet Published Date
Compiler User Guide: Intel Quartus Prime Pro Edition  2018-05-07
Design Optimization User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Third-party Synthesis User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Design Constraints User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Block-Based Design User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Partial Reconfiguration User Guide: Intel Quartus Prime Pro Edition 2018-05-07
DSP Builder for Intel® FPGAs --
Application Notes Published Date
AN 738: Intel Arria® 10 Device Design Guidelines 2017-06-30
Training and Videos
Title Published Date
Design Block Reuse in the Intel® Quartus® Prime Pro Software OBBDR100
Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Design Partitioning OIBBC101
Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Introduction OIBBC100
Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Timing Closure & Tips OIBBC102
Documentation
User Guides / Device Overview / Device Datasheet Published Date
Timing Analysis Overview 2017-11-06
Timing Analyzer User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Quartus II Scripting Reference Manual 2013-07-01
SDC and TimeQuest API Reference Manual 2009-12-01
Intel Quartus Prime Timing Analyzer Cookbook 2017-11-06
Application Notes Published Date
AN 366: Understanding I/O Output Timing for Altera® Devices 2006-07-01
AN 471: High-Performance FPGA PLL Analysis with TimeQuest 2007-08-01
AN 433: Constraining and Analyzing Source-Synchronous Interfaces 2016-05-01
AN 775: I/O Timing Information Generation Guidelines 2016-10-31
Design Examples
Title Published Date
Timing Analyzer Design Examples 2010-01-01
Known Issues
Training and Videos
Title Published Date
Getting Started with the TimeQuest Timing Analyzer 2014-11-24
Timing Analyzer: Introduction to Timing Analysis --
Advanced Timing Analysis with TimeQuest --
Timing Analyzer: Quartus® Prime Integration & Reporting --
Timing Analyzer: Required SDC Constraints --
Timing Analyzer: Timing Analyzer GUI --
The Intel® Quartus Prime Software Design Series: Timing Analysis with Timing Analyzer --
Intel FPGA Wiki
Title Published Date
Source Synchronous Interfaces between Altera® FPGAs 2015-11-26
Source Synchronous Analysis with TimeQuest 2012-02-26
Constraining Edge Aligned Source Synch input interfaces in TimeQuest 2014-10-21
Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest 2014-10-21
TimeQuest User Guide 2010-12-09
DDR Timing with TimeQuest 2011-01-18
Documentation
User Guides / Device Overview / Device Datasheet Published Date
Programmer User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Analyzing and Debugging Designs with System Console 2017-11-06
Design Debugging Using In-System Sources and Probes 2017-11-06
Debug Tools User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Intel® Quartus® Prime Standard Edition Handbook Volume 3 Verification 2017-11-06
Altera® Virtual JTAG (altera_virtual_jtag) IP Core User Guide 2016-10-31
Analyzing and Debugging Designs with System Console 2014-06-30
FPGA-Adaptive Software Debug and Performance Analysis --
System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug --
ByteBlaster II Download Cable User Guide --
Intel FPGA USB Download Cable User Guide 2016-10-31
Intel FPGA Download Cable II User Guide --
EthernetBlaster Communications Cable User Guide 2016-10-28
BSDL Support --
Application Notes Published Date
AN 827: Unified Tool for Generating Programming Files 2018-05-07
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files --
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer --
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile 2017-05-08
AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC 2015-05-11
AN 541: SerialLite II Hardware Debugging Guide --
AN 543: Debugging Nios II Software Using the Lauterbach Debugger --
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench --
AN 624: Debugging with System Console over TCP/IP --
Design Examples
Title Published Date
Arria® 10 DDR3 x40 with EMIF Debug Toolkit --
Debugging Nios® II Systems with the SignalTap II Embedded Logic Analyzer on Embedded Systems, Cyclone® III --
Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer on Embedded Systems, Nios II--Cyclone III Edition --
Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer on Stratix® IV --
Debugging with System Console over TCP/IP (SCTCP) Design Example --
How to Debug HPS SPI Using SignalTap II --
MAX® 10 DDR3 Design with Debug Feature --
MAX® 10 LPDDR2 Design with Debug Feature --
PCIe* In-Simulation Status Debug for PIPE Interface --
Remote System Debug --
System Console Debugging --
Known Issues
Training and Videos
Title Published Date
Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction OVJTAG1110
Debugging JTAG Chain Integrity ODJTAG1110
On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices OMEM1124
SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals OEMB5501
The Quartus® Software Debug Tools IDSW135
JTAG Chain Debugger Tool --
Quartus In Systems Sources and Probes Debug Flow --
U-Boot Console and FDT Debug --
Setting Up and Debugging Quartus Floating Licenses --
Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs --
Arria 10 Temperature Sensor Debug --
Using the Soft Nios® processor to Debug Arria 10 External Memory Interfaces --
How to Debug Altera® Triple Speed Ethernet Link Synchronization Issue --
Quick Signal Tapping with SignalProbe in the Altera Quartus II Software --
Understanding and Utilizing USB Blaster and JTAG to Configure Intel FPGAs --
Running the SoC Preloader with the ARM* DS-5* Debugger --
Altera Transceiver Loopback with In-System Sources and Probes --
Debugging Techniques for Qsys and Nios Based Bare Metal Systems --
Intel FPGA Wiki
Title Published Date
Debug Apps --
How to Debug HPS SPI Using SignalTap II 2015-12-24
Development Boards and Kits --
DisplayPort MegaCore Debug Checklist --
System Console --
Low Latency Ethernet 10G MAC Debug Checklist --
SoC Debugging FTA 2016-11-29
SDI II MegaCore Debug Checklist --
10Gbps Ethernet MAC Debug Checklist --
Arria® 10 EMIF Debug GUI 2016-11-29
Arria 10 Debugging Multiple EMIFs --
Software Downloads
Title Published Date
Altera® Programming Software --
Altera Jam™ STAPL Software  --
Cable and Adapter Drivers Information --
MAX+PLUS® II Software --
Altera Legacy Software --
Intel Quartus® Prime Software Stand-Alone Programmer --
Altera Stand-Alone Programmer Software --
Intel Quartus Prime Software  --

Still Have Questions?

If you are unable to find something on this page, go though a list of knowledge base articles published on the Knowledge Base Center or raise a service request using Intel Premier Support.

Explore Other Developer Centers

For other design guidelines, visit the following Developer Centers:

  • Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Intel® FPGAs and SoC FPGAs
  • Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs
  • System Architect Developer Center - Contains information on how Intel® FPGAs can add value to your system design 

Click on the following links below to explore other Developer Centers now.

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