User Guides / Device Overview / Device Datasheet Published Date
Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook 2017-12-15
Intel Arria 10 Device Datasheet 2018-01-09
Intel Arria 10 Device Overview 2018-01-17
Intel Arria 10 GX/GT Device Errata and Design Recommendations 2017-12-20
Intel Arria 10 Transceiver PHY User Guide 2017-11-06
Power Sequencing Considerations for Intel Cyclone® 10 GX, Intel Arria 10, and Intel Stratix® 10 Devices 2017-05-08
Altera® I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide 2017-06-16
Intel FPGA Chip ID IP Cores User Guide 2017-12-11
Intel Arria 10 External Memory Interfaces IP User Guide 2017-11-06
Intel Arria 10 External Memory Interfaces IP Design Example User Guide 2017-11-06
Intel Arria 10 External Memory Interface IP Core Release Notes 2017-05-08
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide 2017-12-15
Intel FPGA Voltage Sensor IP Core User Guide 2018-02-09
Early Power Estimator for Intel Arria 10 FPGAs User Guide 2016-11-07
Intel FPGA Temperature Sensor IP Core User Guide 2017-09-14
Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines 2017-06-16
Intel FPGA Parallel Flash Loader IP Core User Guide 2017-11-06
Altera ASMI Parallel II IP Core User Guide 2017-05-08
Altera ASMI Parallel IP Core User Guide 2017-05-31
Altera Remote Update IP Core User Guide 2017-04-10
Application Notes Published Date
AN 556: Using the Design Security Features in Intel FPGAs 2017-12-18
AN 496: Using the Internal Oscillator IP Core 2017-11-06
AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families 2017-11-06
AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines 2017-05-08
AN 711: Power Reduction Features in Intel Arria 10 Devices 2017-05-08
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 Devices 2016-05-05
AN 737: SEU Detection and Recovery in Intel Arria 10 Devices 2017-03-15
AN 738: Intel Arria 10 Device Design Guidelines 2017-06-30
AN 742: PMBus SmartVID Controller Reference Designs 2017-05-08
AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus® Prime Software 2017-12-18
Title  Published Date
Arria® 10 LVDS Basic Design Examples 2017-03-15
Arria 10 Voltage Sensor 2014-12-16

External Memory Interface

Ethernet

PCI Express*

Other Serial IP

Digital Signal Processing (DSP)

Embedded

User Guides Published Date
Embedded Peripherals IP User Guide 2017-11-06

Audio and Video

User Guides Published Date
Intel® FPGA SDI II IP Core User Guide 2017-11-06

External Memory Interface

Ethernet

PCI Express*

Other Serial IP

Title Published Date
Intel® FPGA IP Release Notes 2017-11-30

External Memory Interface

Title Course ID
Guide for New External Memory Interface (EMIF) Spec Estimator --
External Memory Interface Device Selector Tutorial --
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2 --
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2 --
DDR4 Ping Pong PHY --
How to Generate Arria® 10 EMIF Example Design --
Creating Multiple Arria 10 Memory Designs with Qsys --
Simulating an Arria 10 External Memory Interface --
Arria 10 FPGA & SoC EMIF --
How to Implement Package Deskew in External Memory Interface Design in Stratix® 10 and Arria 10 --
Board Timing for Arria 10 EMIF IP --
Implementing Over Constraint in Arria 10 External Memory Interface --
Automated Check of Altera® External Memory Interfaces Board Layout Guidelines --
Arria 10 External Memory Interface Toolkit --
Arria 10 EMIF Example Traffic Generator --
Using the Soft Nios® Processor to Debug Arria 10 External Memory Interfaces --
Arria 10 External Memory Interface Read and Write 2-D Eye Diagram --
External Memory Interface Driver Margining Part 1 --
External Memory Interface Driver Margining Part 2 --
How to Build RLDRAM3 EMIF Design for Arria 10 Development Kit and Test the Calibration Status Using EMIF Toolkit --
Altera® PHYLite Demo Part 1 --
Altera PHYLite Demo Part 2 --
Building Parallel Interfaces with Altera PHYLite IP --
How to Perform Group Pin Placement for PHYLite IP --
Generating PHYLite Example Design Simulation in ModelSim* in 16.1 with Arria 10 --
How to Create the OCT Block for Calibrated Termination I/O Buffer in Altera PHYLIte IP --
How to Estimate Arria 10 / Stratix 10 PHYLite Input and Output Path Latency --
How to Configure A10 /S10 Altera PHYLite Input and Output Delay Constraints --
How to Configure PHYLite IP Dynamic Reconfiguration Timing Settings --
Introduction to Memory Interfaces IP in Arria 10 & Stratix 10 Devices  0MEM1121
Integrating Memory Interfaces IP in Arria 10 Devices  0MEM1122
Verifying Memory Interfaces IP in Arria 10 Devices 0MEM1123
On-Chip Debugging of Memory Interfaces IP in Arria 10 Devices  0MEM1124

PCI Express*

Other Serial IP

Title Published Date
Altera® JESD204B IP Quick Start Video 2016-05-03

External Memory Interface

The Intel® Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these template, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Edition Handbook.

The Intel® Quartus® Prime design software also comes with Intel® High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for Intel® FPGA products.

Title Published Date
Timing Analyzer Design Examples 2010-01-01
User Guides / Device Overview / Device Datasheet Published Date
Programmer User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Analyzing and Debugging Designs with System Console 2017-11-06
Design Debugging Using In-System Sources and Probes 2017-11-06
Debug Tools User Guide: Intel Quartus Prime Pro Edition 2018-05-07
Intel® Quartus® Prime Standard Edition Handbook Volume 3 Verification 2017-11-06
Altera® Virtual JTAG (altera_virtual_jtag) IP Core User Guide 2016-10-31
Analyzing and Debugging Designs with System Console 2014-06-30
FPGA-Adaptive Software Debug and Performance Analysis --
System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug --
ByteBlaster II Download Cable User Guide --
Intel FPGA USB Download Cable User Guide 2016-10-31
Intel FPGA Download Cable II User Guide --
EthernetBlaster Communications Cable User Guide 2016-10-28
BSDL Support --
Application Notes Published Date
AN 827: Unified Tool for Generating Programming Files 2018-05-07
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder SystemsDesign files --
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer --
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile 2017-05-08
AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC 2015-05-11
AN 541: SerialLite II Hardware Debugging Guide --
AN 543: Debugging Nios II Software Using the Lauterbach Debugger --
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench --
AN 624: Debugging with System Console over TCP/IP --

Still Have Questions?

If you are unable to find something on this page, go though a list of knowledge base articles published on the Knowledge Base Center or raise a service request using Intel Premier Support.

Explore Other Developer Centers

For other design guidelines, visit the following Developer Centers:

  • Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Intel® FPGAs and SoC FPGAs
  • Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs
  • System Architect Developer Center - Contains information on how Intel® FPGAs can add value to your system design 

Click on the following links below to explore other Developer Centers now.