This design example demonstrates the compilation and simulation flow for implementating SerialLite II (SLII) intellectual property (IP) core in Stratix® V devices.
For Stratix V, Arria® V, and Cyclone® V devices, the generated SLII core does not include transceiver core. You must instantiate the Custom PHY IP core separately and integrate it together with the SLII core.
This demonstration is targeted for Stratix V and Arria V devices.
Table 1 lists four different variances of the Custom PHY IP core that are used with the SLII core.