This design example demonstrates the compilation and simulation flow for implementating SerialLite II (SLII) intellectual property (IP) core in Stratix® V devices.
For Stratix V, Arria® V, and Cyclone® V devices, the generated SLII core does not include transceiver core. You must instantiate the Custom PHY IP core separately and integrate it together with the SLII core.
This demonstration is targeted for Stratix V and Arria V devices.
Table 1 lists four different variances of the Custom PHY IP core that are used with the SLII core.
Table 1. Custom PHY IP Core Variances
FPGA Fabric Transceiver Interface Width
Blocks Enabled
SLII Data Rate (Mbps)
32
(Tsize = 4)
Word alignment mode: Manual
Word alignment pattern: 10'b0101111100 (10h'17C)
8B/10B encorder/decoder
3,126 to 6,375
16
(Tsize = 2)
Word alignment mode: Manual
Word alignment pattern: 10'b0101111100 (10h'17C)
8B/10B encorder/decoder
1,000 to 3,125
16
(Tsize = 2)
Word alignment mode: Automatic synchronization state machine
Word alignment pattern: 10'b0101111100 (10h'17C)
Rate match FIFO
Rate match insertion/deletion +ve disparity pattern: 20'b00110000111010000011 (20'h30E83)
Rate match insertion/deletion -ve disparity pattern: 20'b11001111000101111100 (20'hCF17C)
8B/10B encorder/decoder
3,800 to 5,000
8
(Tsize = 1)
Word alignment mode: Automatic synchronization state machine
Word alignment pattern: 10'b0101111100 (10h'17C)
8B/10B encorder/decoder
622 to 2,500
Compilation Flow
Instantiate the SLII core and run the constraints file.
Instantiate the Custom PHY IP core.
Integrate the SLII core and Custom PHY IP core.
Create the Synopsys® Design Constraint (SDC) file for the design integration between SLII core and Custom PHY IP core.
The SDC file used for Custom PHY IP must have the correct PLL reference clock frequency.
The transceiver clock name for the Custom PHY IP‘s tx_clkout and rx_clkout must be used in the asynchronous clock group constraint in the SDC file to integrate design between the SLII core and Custom PHY IP core.
Select your target device for the compilation.
Set the SDC file for integration into the Quartus® Prime or Quartus II project file.
Note that the Transceiver Reconfiguration Controller must be used for offset cancellation purpose in hardware design.
Simulation Flow
Initiate the SLII IP core device under test (DUT) and enable the simulation model option.
Determine the Custom PHY IP core variance by referring to the SLII data rate and transfer size in Table 1, and initiate the Custom PHY IP core accordingly.
A testbench file (<SLII_instance_name>_tb.v) as shown in the figure below will be generated.
Create top.v file (SLII IP core and Custom PHY IP core) and top_sister.v file (SLII sister IP core and Custom PHY sister IP core).
Modify the testbench file as shown in the figure below by replacing the SLII IP core (DUT and sister IP core) with the top files (top.v and top_sister.v). Change the reference design frequency in the testbench file to reflect the selected PLL reference clock frequency in the Custom PHY IP core. The default reference clock frequency in the testbench file is 156.25 MHz.
Modify the Tcl file (<SLII_instance_name>_run_modelsim.tcl) by adding the Custom PHY IP core simulation files into the command line. You can use the updated Tcl file in the design example.
Execute the Tcl file.
Table 2 lists four different variances of SLII design example.
Table 2. SLII IP Core Design Examples
Example files
Port Type
Data Type
Transfer Size
Data Rate
Reference clock
Example1
Bidirectional
Packet (Normal data packet only)
4
6.375 Gbps
255 MHz
Example2
Receiver only
Packet (Normal data packet and priority data packet)
2
3.125 Gbps
156.25 MHz
Example3
Bidirectional
Streaming
2
5.000 Gbps
125 MHz
Example4
Transmitter only
Streaming
1
622 Mbps
62.2 MHz
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