Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature
The objective of this design example is to showcase the way to constraint the TSE_RGMII. This design example is only applicable when the delay feature (90 degree shift) of TX_CLK and RX_CLK of external PHY are turned on. It can run on 3 different speeds which are 10 MHz, 100 MHz, and 1000 MHz.
Assumption is made that the user is familiar with the Triple Speed Ethernet intellectual property (IP) Core, ALTDDIO, ALTPLL, TimeQuest and Static Timing Analysis, and double data rate (DDR) source synchronous concept.
How to Constraint
Select the method of interface constraint: system centric method or FPGA centric method.
Different method requires different formula to calculate the delay value in the set_input_delay and set_output_delay command
This design example use system centric method
Decide whether to turn on or turn off the delay feature (±90 degree shift) of external PHY as it will determine the type of alignment between the clock and data.
90 degree shift -> center aligned
No shift -> edge aligned
This design example is applicable to delay feature of TX and RX of external PHY are turned on (90 degree shift) only
Determine the desired launch and latch relationship.
There are 4 types of launch and latch relationship.They are Rise-Rise (RR), Rise-Fall (RF), Fall-Rise (FR) and Fall-Fall (FF) relationship
RGMII specification state that the LSB of data [3:0] will be sending out at the rising edge first and MSB of data [7:4] is sent out followed by the falling edge
The design of TSE with RGMII interface will capture the data at the rising edge first then followed by falling edge. It implies that the clock needs to be shifted +90 degree instead of -90 degree
Desired setup launch and latch relationship (Arrow in red): RR and FF
Desired hold launch and latch relationhip (Arrow in blue): FR and RF
Figure 2. Lauch Clock and Latch Clock Relationship
Constraint the RGMII Interface.The Synopsys Design Constraints (SDC) is based on the design and application.However, there are some main SDC needed for RGMII interface.
the clock that latch the data inside the FPGA prior to transmit to external PHY
the clock with 90 degree phase shift that latch the data at the external PHY
It is unwanted relationship not to be analyzed in timing analysis. In this design example, unwanted relationship for the setup is RF and FR while unwanted relationship for the hold is RR and FF
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