This design demonstrates how to instantiate ALTGX or ALTLVDS separately from the Triple Speed Ethernet (TSE) MegaCore® function instance.
This design instantiates TSE MegaCore without selecting the GXB or LVDS I/O. ALTGX or ALTLVDS is instantiated separately and configured to interface with the TSE physical coding sublayer (PCS) through a ten-bit interface (TBI), as shown in Figure 1.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.
Files in the download include:
- s4gx_tse_lvds.qar - Archive of TSE Design using ALTLVDS
- s4gx_tse_gxb.qar - Archive of TSE Design using ALTGX
Figure 1. Conceptual Block Diagram for TSE MAC + PCS Interface with ALTGX or ALTLVDS Instance through TBI