Configure ALTGX with the following settings:
- Under the General tab, set protocol to Basic
- Under the General tab, set channel width to 10
- Under the General tab, set data rate to 1.25Gbps and input clock frequency to 125MHz
Note: Instantiate ALTGX_RECONFIG block for Stratix® IV GX and Arria® II GX devices.
For TSE to ALTGX interface, connect the following signals:
- tbi_rx_clk (TSE) to rx_clkout (ALTGX)
- tbi_rx_d[9..0] (TSE) to rx_dataout[9..0] (ALTGX)
- tbi_tx_clk (TSE) to tx_clkout (ALTGX)
- tbi_tx_d[9..0] (TSE) to tx_datain[9..0] (ALTGX)
Configure ALTLVDS RX with the following settings:
- Under the General tab, enable Dynamic Phase Alignment (DPA) mode
- Under the General tab, set deserializer factor to 10
- Under the Frequency/PLL settings tab, set data rate to 1.25Gbps and input clock frequency to 125MHz
- Under the DPA settings 1 tab, check ‘rx_divfwdclk’ output port and bypass the DPA FIFO option
For the TSE to ALTLVDS interface, connect the following signals:
- tbi_rx_clk (TSE) to rx_divfwdclk (ALTLVDS)
- tbi_rx_d[0..9] (TSE) to rx_out[9..0] (ALTLVDS)
- tbi_tx_clk (TSE) to 125MHz system clock
- tbi_tx_d[0..9] (TSE) to tx_in[9..0] (ALTLVDS)
Note: The TSE TBI data bus to LVDS data bus connection is in reverse order.
Note: For ALTGX and ALTLVDS reset sequence, please refer to the device handbook.
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