The Process Flow
- Port initialized (RapidIO link up)
- RapidIO initialization
- Send write packets (similar to NWrite transactions)
- System Controller A commands Packet Generator to send packets to RapidIO A
- Packets are sent across the link to RapidIO B and stored in RAM by System Controller B
- The write packet can be adjustable for payload size and number of packets
- Send doorbell messages
- System Controller A commands Packet Generator to send doorbell messages to RapidIO A
- Doorbell messages are sent across the link to RapidIO B. They are received and processed by Doorbell Processor in System Controller B
- The doorbell messages carry instructions which are interpreted by the Doorbell Processor. There are two example instructions: Invert Packets and Retrieve Data
- For Invert Packets, Doorbell Processor reads data from RAM, inverts it, and stores it back in RAM (can be in different address)
- For Retrieve Data, Doorbell Processor reads data from RAM and sends it back to RapidIO A
- These two instructions show that RapidIO A can initiate action items for RapidIO B to execute. You may use this to create specific instruction packets to your own implementations
This low-level design implementation can also be used as an example to do the following customizations:
- Add or change packet parameters or format (e.g. address-payload-address-payload) or data streaming
- Handle different feature sending sequence in one port instead of on round-robin basis in Transport Layer
- Support custom functions which are generally not included by the RapidIO MegaCore® function
However, to handle the customizations stated above, users need to fill the Physical and Transport Layer fields of a packet header manually. Other steps, such as packet format decoding and controlling the packet traffic, are also required for the smooth operation of this Avalon-ST Pass-Through Interface.
Download the .zip file used in this design example: avST_passthr_interface.zip
Note: This design example has been tested in simulation.
Design Examples Disclaimer
These design examples may only be used within Intel® Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.