Compact Configuration Design Example for the Nios® II Processor

The Nios® II processor compact configuration design example demonstrates reconfiguration of Cyclone® III FPGAs using Nios II embedded processor and the remote update controller. The design is built to use the minimal amount of FPGA resources. Due to its compactness, the design can be added to your existing system to add the reconfiguration feature. To learn more about the design example, refer to application note AN 548: Nios II Compact Configuration System for Cyclone III (PDF).

Using This Design Example

To run this example, download and unzip it to your hard drive. Follow the directions in AN 548 to run the design.

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.

Design Specifications

The design contains the following components:

  • Nios II processor (Nios II/e economic core)
  • On-chip random access memory (RAM)
  • Phase-locked loop (PLL)
  • Remote update controller
  • Tri-state bridge
  • CFI flash controller
  • LED parallel I/O (PIO)
  • Push-button PIO
  • System ID peripheral

This design targets the Cyclone III FPGA Starter Kit and Nios II Embedded Evaluation Kit (NEEK).

Figure 1. Compact Configuration Design Example

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.