The Nios® II multiprocessor design example demonstrates the use of multiple Nios II processors in an Altera® FPGA. Although this example is primarily aimed at demonstrating a properly constructed hierarchical hardware system, it also contains the software to exercise the inter-processor coordination capabilities of the system.
This example implements the classic “dining philosophers” synchronization problem. Imagine five philosophers seated at a round table. A single chopstick is positioned between each philosopher. Each philosopher tries first to grab the chopstick to his left, and then the chopstick to his right. If both chopsticks are acquired, the philosopher can eat. After a small delay which represents the eating time, each philosopher drops both chopsticks, making them available to his neighboring philosophers. After another small delay, which represents thinking time, the cycle repeats. To prevent deadlock, if any philosopher cannot grab the right chopstick immediately after grabbing the left chopstick, he must drop the left chopstick and try again later.
Created with Qsys, the hierarchical hardware design dedicates five processors to implement each of five dining philosophers and five hardware mutexes to implement each of five chopsticks. A sixth Nios II processor and an on-chip RAM reside in the top level, along with a JTAG UART and timer. Each of the five subsystems shares the top-level on-chip RAM and contains a Nios II processor, JTAG UART, timer, and mutex, which is a hardware peripheral that provides the processors with mutually exclusive coordination. The Avalon® Memory-Mapped (Avalon-MM) pipeline bridges enable communication between the subsystems and top-level components, and between processors and mutexes located in logically adjacent subsystems connected in a ring.
The dining_philosophers.c software runs on each of five subsystem processors, implementing the thinking, eating, and chopsticks acquisition and release processes. The top-level processor executes philosophers_monitor.c, accepting numeric commands to acquire any mutex. This prevents both logically adjacent “philosopher” processors from eating until that “chopstick” mutex is released.
Hardware Design Specifications
- Board support
- Altera Cyclone® III 3C120 FPGA development board
- Nios II/f processor cores, debug-enabled, with 4-KB instruction cache and 2-KB data cache: 6
- System timers: 6
- On-chip RAM: 64 KB
- JTAG UART peripherals: 6
- Mutex peripherals: 5
- System ID peripheral: 1
This design example is based on the system constructed in the Creating Multiprocessor Nios II Systems Tutorial (PDF). For detailed information about implementing Nios II multiprocessor systems, refer to the tutorial mentioned above.
Figure 1. Hierarchical Nios II Multiprocessor System Block Diagram
Download the file used in this example:
The .zip file contains all the necessary hardware and software files to reproduce this example, as well as a readme.txt file.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
- Creating Multiprocessor Nios II Systems Tutorial (PDF)
- Mutex Core chapter of the Embedded Peripherals IP User Guide (PDF)
- Nios II processor literature
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