Nios II High-Performance Example with Bridges

The Nios® II high-performance example illustrates how you can use bridges in your design to control the topology of your system. By controlling the system's topology, you can also increase the fMAX of your design.

This design example is based on the full-featured design provided in the Nios II Embedded Design Suite (EDS) and is enhanced to run at a higher clock speed without sacrificing features. Floating-point math hardware has been added to the design to accelerate single precision floating-point math operations.

Download high-performance full-featured ZIP (699 KB)

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.

Design Specifications

  • Nios II/f core (with floating-point math hardware)
  • JTAG debug module (level 1)
  • On-chip tightly coupled data memory (8 Kbyte)
  • On-chip tightly coupled instruction memory (4 Kbyte)
  • DDR SDRAM controller (32 Mbyte)
  • SSRAM controller (2 Mbyte)
  • CFI flash memory interface (16 Mbyte)
  • DMA controller
  • EPCS controller (with bootloader)
  • UART (RS-232)
  • Two timers
  • Ethernet interface
  • LED parallel I/O (PIO)
  • Seven-segment display PIO
  • Push-button PIO
  • LCD display interface
  • Performance counter
  • System ID peripheral

Figure 1. Nios II High-Performance Example with Bridges

Figure 1. Nios II High Performance Example With Bridges
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  1. TCIM = tightly coupled instruction master
  2. TCDM = tightly coupled data master
  3. RM = read master
  4. WM = write master


Nios II Development Kit Stratix® II RoHS Edition

  • 150-MHz clock frequency
  • 167 MIPS* (*Dhrystones 2.1 benchmark) with .text, .rodata, .rwdata in SSRAM and heap, stack in tightly coupled data memory

Nios II Development Kit Cyclone® II Edition

  • 100-MHz clock frequency
  • 107 MIPS* (*Dhrystones 2.1 benchmark) with .text, .rodata, .rwdata in SSRAM and heap, stack in tightly coupled data memory

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