Nios II Hardware Development Design Example

The Nios^® II hardware development tutorial introduces you to the system development flow for the Nios II processor. The design example accompanying this tutorial serves as a basic starting block for you to build a system as shown in Figure 1. Using the Quartus^® Prime or Quartus II software and the Nios II Embedded Design Suite (EDS), you can build a Nios II hardware system design and create a software program that runs on the Nios II system and interfaces with components on Altera^® development boards.

Hardware Design Specifications

• Nios II/s core with JTAG debug module
• JTAG-UART
• Timer
• LED parallel I/Os (PIOs)
• System ID peripheral
• On-chip RAM

Using This Design Example

To run this example, download the niosII_hw_dev_tutorial.zip and unzip it to your hard drive. Then, follow these instructions in the application note below:

• Nios II Classic: Nios II Hardware Development Tutorial
• Nios II Gen2: Nios II Gen 2 Hardware Development Tutorial

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Related Links

For more information on Nios II processor hardware, go to:

• Nios II Processor Reference Handbook (PDF)

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.