This design example shows the Hardware Abstraction Layer (HAL) software device driver development process for the UART. Using the Nios® II Embedded Evaluation Kit (NEEK), Cyclone® III Edition as the hardware platform, this example shows the various software development stages needed to develop a HAL software device driver for Nios II embedded processor.
Hardware Design Specifications
The hardware design used in this example targets NEEK, Cyclone III Edition. Key peripherals in this design includes:
- Nios II/f CPU core
- 16-kilobytes (KB) on-chip RAM
- JTAG UART
- System identification (ID)
- Interval timer
Using This Design Example
For information on how to run the design example, please refer to AN459: Guidelines for Developing a Nios II HAL Device Driver (PDF).
Download the files used in this example: an459-design-files.zip.
Design Examples Disclaimer
These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.