This design example shows you how to debug your system design using the dynamic information provided by the Nios® II processor during software execution. This design example demonstrates the use of the Nios II plug-in, the SignalTapTM II logic analyzer, and the Nios II Software Build Tools for Eclipse to trigger on, capture, and trace the signals.
Get the necessary files for this design example:
- an446_signal_tap_test.zip – contains the files required to run the design example
- AN 446: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer (PDF) – provides details and instructions on running the design example
- Nios II Ethernet Standard design example – provides the hardware platform for the design
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.