Nios II CRC Acceleration Design Example


The cyclic redundancy check (CRC) algorithm detects the corruption of data during transmission, and detects a higher percentage of errors than a simple checksum. The CRC calculation consists of an iterative algorithm involving XORs and shifts that execute much faster in hardware than in software. This design uses the CRC-32 standard. It is implemented as a custom component alongside a Nios® II embedded processor. The design achieves over 5 Gbps throughput, demonstrating the levels of performance improvement that can be achieved by performing the function in hardware.


  • Supports any CRC algorithm between 1–128 bits
  • CRC component throughput of 32 bits per MHz
  • 8-, 16-, 24-, and 32-bit datapaths
  • Up to 2000x speed improvement over a software-only implementation
  • Low latency performance of 0 cycle write latency and 1 cycle read latency
  • Two example designs targeting Stratix® II and Cyclone® II FPGAs

Demonstrated Altera Technology

Block Diagram

Figure 1 shows the Avalon® CRC component block diagram.

Figure 1. Avalon CRC Component Block Diagram


  1. Data path = crc_width.

Using This Design Example

Download the CRC Example Design (.zip file)

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

The .zip file contains all the necessary hardware and software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for re-building the design.

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