Figure 1: Checksum Accelerator Block Diagram
All of the components contain Avalon® Interfaces and can be connected to each other to form the checksum accelerator. You can replace any of the components with another functionally-equivalent component. For example, you can replace the controller component with a state machine that runs on its own.
In this example, the controller is connected to a Nios II processor. The processor communicates the base address of the memory buffer and data length to the controller component. Once the read master knows this information, it will continuously read data from memory and pass it to the checksum calculator for the checksum operation.
When the checksum calculation has been performed on all data, the calculator will issue a valid signal along with the checksum result to the controller. The controller will then set the DONE bit in the status register and also assert the interrupt signal. You should only read the result from the controller when the DONE bit and the interrupt signal are asserted.
This accelerator component supports both 32-bit and 64-bit data checksum calculation. The speedup factor for the hardware-accelerated checksum implementation versus the software checksum is up to 30 for 32-bit data, and up to 60 for 64-bit data.
This design example is targeted to be used with the Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition.
Hardware Design Specifications
The design contains the following components:
Nios II processor (Nios II/f fast core)
DDR SDRAM high-performance controller
Avalon Memory-mapped pipeline bridge
Push-button parallel I/O (PIO)
System identification (ID) peripheral
Using This Design Example
To run this example, download the altera_avalon_checksum_de.zip and unzip it to your hard drive. Then, follow the instructions in the readme.doc found in the .zip file.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
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