This Mandelbrot design example demonstrates the use of the Nios® II embedded processor C-to-Hardware (C2H) acceleration compiler. In this example, the C2H compiler transforms the C-based implementation of the Mandelbrot algorithm into hardware. This design also contains a video controller to display full-motion video of the calculated pixel values.
The Mandelbrot pattern has become one of the most well known fractals because of its complex patterns and processor-intensive implementation. The algorithm operates in the complex plane where the x-axis represents the real component, and the y-axis represents the imaginary component. The example performs movements to different regions of the plane and also zooms in and out, creating full-motion video.
This example makes full use of parallelism by performing coordinate calculations in software while the hardware accelerators are in use. This is done by triple buffering the video data in DDR SDRAM and using the Nios II embedded processor to coordinate the data flow. Every time a full frame buffer is rendered by the hardware accelerator, the data is then managed by the processor to overlay benchmark data and notify the video controller that a new buffer is ready for display.
Using This Design Example
This design targets the following development kits:
- Nios II Embedded Evaluation Kit, Cyclone® III FPGA Edition
- Nios II Embedded Development Kit, Cyclone III FPGA Edition
Download the Nios II C2H Mandelbrot Design Example (.zip file)
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.
The .zip files contain all the necessary software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for rebuilding the design targeting an existing hardware design.
Figure 1 shows the block diagram of the C2H Compiler Mandelbrot design example.
Figure 1. C2H Compiler Mandelbrot Design Example
C2H Compiler Accelerated Results
The C2H compiler-accelerated Mandelbrot algorithm results in a speed improvement of at least 60x compared to the same algorithm running on the fastest Nios II processor using compiler optimization level 2 (-O2). This speed increase is because of the parallelism and fast iteration speeds that hardware can provide, which are not possible from a general-purpose processing unit.
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