The template provided contains an Avalon® Memory-Mapped (MM) Verilog module bundled as an SOPC Builder-ready component. The component is parameterizable, allowing you to select functionality on a per-register basis. You can use the component with any Altera® device family supported by SOPC Builder. The component is Verilog based, so you can add your own functionality or simply use it as a reference. For ease of use, the component uses Tcl callbacks to allow you to make setting changes automatically in a GUI environment.
You can use this component as a replacement for the PIO component that is available from SOPC Builder. This component implements the same logic, but it is duplicated for up to 16 I/O pairs. This component also supports data widths ranging from 8 to 1,024 bits with an optional loopback mode to allow software developers to readback the output contents. Version 2.0 of this component supports input ports (or read register files) with interrupt capabilities for data widths ranging from 8 to 32 bits. Interrupts are generated by the rising edge data toggle at the input ports.
Figure 1. Component Block Diagram
Each I/O pair is capable of the access types shown in Table 1.