The variable integer rate decimation filter design example demonstrates how to use the Intel® DSP Builder Advanced Blockset (DSPB-AB) to implement a decimation filter that can change its decimation rate at run time. It also supports multiple channels and exploits automatic folding of DSPB-AB to generate register transfer level (RTL) code that maximizes hardware reuse for resource saving. The current design supports decimation rates of 1, 2, 4, 8, and 16. However, you can easily modify the design to support other integer decimation rates.
You can efficiently implement conventional decimation by M filters through polyphase decomposition with an input commutator and M parallel paths. Each path is a polyphase of the original prototype filter. If the input commutator skips every other phase, instead of going through all M paths, the decimation rate becomes M/2, and so on.
In the real design, instead of having a commutator and a parallel bank of finite impulse response (FIR) filter paths, we implement only one polyphase FIR filter, where the coefficients corresponding to the polyphases change every cycle at the input sample rate. It has the same effect as delivering input samples successively to a parallel bank of polyphases. We store the polyphase coefficients in memory, and use an input accumulator like the one used in a numerically controlled oscillator (NCO) to control which phase is currently being read out and sent to the FIR filter path. The step size of the phase accumulator controls how fast the system cycles through the polyphases, hence the decimation rate. The overflow signal of the accumulator indicates when the phases have been cycled through. When it asserts, a valid output sample is generated at the lower sample rate.
The architecture of the algorithm is shown in Figure 1.
