In digital up-conversion, baseband signals are interpolated to intermediate frequency (IF), then digitally modulated by IF sinusoidal carriers. According to the Nyquist theory, the IF carrier frequency is limited to half of the IF circuits sampling frequency. This design example demonstrates how to achieve digital up-conversion with IF carrier frequency that is higher than the Nyquist frequency. The key is to exploit the periodicity of sinusoidal signals and the high sampling frequency of the low voltage differential signal (LVDS) serializer that is embedded on Altera® FPGAs. Modulating IF signals to higher carrier frequencies takes full advantage of the high sampling rate of modern digital-to-analog converters (DAC) and eases the requirement for analog voltage-controlled-oscillators (VCO) and mixers.
Figure 1 shows the block diagram of the polyphase digital up-conversion system. The shaded box contains modules used in this design example. By default, the polyphase filters operate at 100 MHz. With four polyphase components, the output of the LVDS transmitter has a data rate of 400 MHz. In a conventional up-conversion modem, the IF carrier frequency is limited to no more than 50 MHz by the clock frequency of the numerically controlled oscillator (NCO). By exploiting aliasing, however, the output carrier frequency in this design example is centered at 160 MHz.