VHDL: Unsigned Multiply-Adder

This example describes an 8-bit unsigned multiply-adder design with registered I/O ports in VHDL. Synthesis tools detect multiply-adder designs in HDL code and infer altmult_add megafunction.

Figure 1. Unsigned Multiply-Adder Top-Level Diagram

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Table 1. Unsigned Multiply-Adder Port Listing

Port NameTypeDescription
a, b, c, dInput8-bit inputs to multiply-adder unit
clkInputClock
aclrInputAsynchronous clear
resultOutput16-bit output of multiply-adder unit

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