VHDL Templates for State Machines

This page consists of design examples for state machines in VHDL. A state machine is a sequential circuit that advances through a number of states. The examples provide the HDL codes to implement the following types of state machines:

  • 4-State Mealy State Machine

The outputs of a Mealy state machine depend on both the inputs and the current state. When the inputs change, the outputs are updated without waiting for a clock edge.

  • 4-State Moore State Machine

The outputs of a Moore state machine depend only on the present state. The outputs are written only when the state changes (on the clock edge).

  • Safe State Machine

This example uses the syn_encoding synthesis attribute value safe to specify that the software should insert extra logic to detect an illegal state and force the state machine's transition to the reset state.

  • User-Encoded State Machine

This example uses the syn_encoding synthesis attribute to apply specific binary encodings to the elements of an enumerated type.

Download the files used in this example:

Each zip download includes the VHDL file for the state machine and its top level block diagram.

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

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These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.