VHDL: Single-Port RAM

This example describes a 64-bit x 8-bit single-port RAM design with common read and write addresses in VHDL. Synthesis tools are able to detect single-port RAM designs in the HDL code and automatically infer either the altsyncram or the altdpram megafunctions, depending on the architecture of the target device.

Figure 1. Single-Port RAM Top-Level Diagram

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Table 1. Single-Port RAM Port Listing

Port NameTypeDescription
data[7:0]Input8-bit data input
addr[5:0]Input6-bit address input
weInputWrite enable input
clkInputClock input
q[7:0]Output8-bit data output

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