VHDL: Single-Port RAM

This example describes a 64-bit x 8-bit single-port RAM design with common read and write addresses in VHDL. Synthesis tools are able to detect single-port RAM designs in the HDL code and automatically infer either the altsyncram or the altdpram megafunctions, depending on the architecture of the target device.

Figure 1. Single-Port RAM Top-Level Diagram

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

 

Table 1. Single-Port RAM Port Listing

Port NameTypeDescription
data[7:0]Input8-bit data input
addr[5:0]Input6-bit address input
weInputWrite enable input
clkInputClock input
q[7:0]Output8-bit data output

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.