VHDL: Single Clock Synchronous RAM

This example describes a parameterized single clock synchronous 16-bit x 8-bit RAM with separate read and write addresses in VHDL. Synthesis tools detect single port RAM designs in HDL code and infer altsyncram or altdpram megafunctions depending on target device architecture.

Figure 1. Single Clock Synchronous RAM Top-Level Diagram

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Table 1. Single Clock Synchronous RAM Port Listing

Port NameTypeDescription
dataInput8-bit data input to RAM
clockInputClock
read_addressInput4-bit read address input
write_addressInput4-bit write address input
weInputWrite enable input
qOutput8-bit data output of RAM

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