VHDL: Signed Multiplier

This example describes an 8-bit signed multiplier design in VHDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction.

Figure 1. Signed Multiplier Top-Level Diagram

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Table 1. Signed Multiplier Port Listing

Port NameTypeDescription
a[7:0], b[7:0]Input8-bit data inputs to multiplier unit
result[15:0]Output16-bit data output of multiplier unit

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