VHDL: Preventing Unintentional Latch Creation

This example design in VHDL shows how coding style can prevent unintentional latch generation. When CASE or IF statements do not cover all possible input conditions unwanted latches may be generated to hold the output. Including the final ELSE clause or WHEN OTHERS clause in an IF or CASE statement can prevent this unwanted latch from being generated.

Figure 1. Unintentional Latch Creation Top-Level Diagram

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Table 1. Unintentional Latch Creation Port Listing

Port NameTypeDescription
a, b, cInputBinary inputs
sel[4:0]Input5-bit select input
oputOutputBinary output

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.