VHDL: Dual Clock Synchronous RAM

This example describes a 64-bit x 8-bit dual clock synchronous RAM design with separate read and write addresses in VHDL. Synthesis tools are able to detect RAM designs in HDL code and automatically infer the altsyncram or altdpram megafunctions depending on the target device architecture.

Figure 1. Dual Clock Synchronous RAM Top-Level Diagram

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Table 1. Dual Clock Synchronous RAM Port Listing

Port NameTypeDescription
data[7:0]Input8-bit data input
raddr[5:0]Input6-bit read address input
waddr[5:0]Input6-bit write address input
weInputWrite enable
rclkInputRead clock
wclkInputWrite clock
q[7:0]Output8-bit data output

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