This example describes an 8-bit counter with asynchronous reset input design in VHDL.
VHDL: Counter with Asynchronous Reset
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Table 1. Counter with Asynchronous Reset Port Listing
| Port Name | Type | Description |
clk | Input | Clock input |
| reset | Input | Asynchronous reset |
enable | Input | Count enable |
q[7:0] | Output | 8-bit counter output |
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