VHDL: Counter with Asynchronous Reset

This example describes an 8-bit counter with asynchronous reset input design in VHDL.

Figure 1. Counter with Asynchronous Reset Top-Level Diagram

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Table 1. Counter with Asynchronous Reset Port Listing

Port NameTypeDescription
clkInputClock input
resetInputAsynchronous reset
enableInputCount enable
q[7:0]Output8-bit counter output

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