This example describes a two input parameterized adder/subtractor design in VHDL. The design unit multiplexes add and subtract operations with an
addnsub input. Synthesis tools detect add and subtract units in HDL code that share inputs and whose outputs are multiplexed by a common signal. Software infers
lpm_addsub megafunction for such add/subtract designs.
Table 1. Adder/Subtractor Port Listing
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