VHDL: Adder/Subtractor

This example describes a two input parameterized adder/subtractor design in VHDL. The design unit multiplexes add and subtract operations with an addnsub input. Synthesis tools detect add and subtract units in HDL code that share inputs and whose outputs are multiplexed by a common signal. Software infers lpm_addsub megafunction for such add/subtract designs.

Figure 1. Adder/Subtractor Top-Level Diagram

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Table 1. Adder/Subtractor Port Listing

Port NameTypeDescription
a[4:0], b[4:0]Input4-bit data inputs to adder/subtractor
addnsubInputMultiplexing input for add and subtract operations
result[5..0]Output5-bit output along with 1-bit carry/borrow

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.