VHDL: 8 x 64 Shift Register with Taps

This example describes an 8-bit wide, 64-bit long shift register with equally spaced taps in VHDL. Synthesis tools detect groups of shift registers and infer altshift_taps megafunction depending on the target device architecture.

Figure 1. 8x64 Shift Register Top-Level Diagram

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Table 1. 8x64 Shift Register Port Listing

Port NameTypeDescription
clkInputClock
shiftInputShift enable input
sr_in[7..0]Input8-bit shift register input
sr_tap_one[7:0]Output8-bit output of first tap
sr_tap_two[7:0]Output8-bit output of second tap
sr_tap_three[7:0]Output8-bit output of third tap
sr_out[7:0]Output8-bit shift register output

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.