VHDL: 1x64 Shift Register

This example describes a single-bit wide, 64-bit long shift register in VHDL. Synthesis tools are able to detect groups of shift registers and automatically infer the altshift_taps megafunction. The implementation may be done in device block memory resources depending on the target device architecture.

Figure 1. 1x64 Shift Register Top-Level Diagram

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Table 1 lists the ports in the 1x64 shift register design.

Table 1. 1x64 Shift Register Port Listing

Port NameTypeDescription
sr_inInputShift register input
enableInputShift enable input
clkInputClock input
sr_outOutputShift register output

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.