Verilog HDL: Interfacing 400-MHz QDR II+ SRAM in a Stratix IV FPGA

This design demonstrates a Stratix® IV device interfacing with 18-bit wide QDR II+ SRAM running at 400 MHz.

The design features advanced I/O timing, board trace models, and the SignalTap® II logic analyzer in Quartus® II software. It is mapped to the Stratix IV GX Development Kit.

A walkthrough of the process is described in External Memory Interface Handbook Volume 6, Section II UniPHY Design Tutorial (PDF). Please refer to the Using QDR II and QDR II+ SRAM in Arria II, Stratix III, Stratix IV, and Stratix V Devices chapter for the full design guidelines and flow.

This design includes Tcl files for:

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