This example describes a single-bit wide, 64-bit long shift register in Verilog HDL. Synthesis tools detect groups of shift registers and infer
altshift_taps megafunction depending on the target device architecture.
Table 1. 1x64 Shift Register Port Listing
These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.