Timing Analyzer Example—Clock Enable Multicycle

With the Synopsys Design Constraint (SDC) set_multicycle_path and the get_fanouts commands, you can create a multicycle exception based on an enable register.

Figure 1 shows a simple circuit where register enable_reg is used to create a registered enabled signal for registers din_a_reg[7..0], din_b_reg[7..0], din_x_reg[7..0], din_y_reg[7..0], a_times_b, and x_times_y.

Figure 1. Simple Registered Enable Design

Figure 1. Simple Registered Enable Design

The enable register enable_reg generates an enable pulse that is two times the register’s clock period and, because of it, a multicycle exception must be applied for the correct analysis. A multicycle setup of 2 and a multicycle hold of 1 must be applied to the enable-driven register fed by the register enable_reg. The multicycle exception is applied only to register-to-register paths where the destination register is controlled by enable_reg.

To accomplish it, you can apply the set_multicycle_path exception to all enable-driven registers. This method can typically be tedious, because all enable-driven registers must be specified. Alternatively, the combination of set_multicycle_path and get_fanouts can be used as follows:

#Setup multicycle of 2 to enabled driven destination registers

set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*] \

-through [get_pins -hierarchical *|*ena*]] -end -setup

#Hold multicycle of 1 to enabled driven destination registers

set_multicycle_path 1 -to [get_fanouts [get_pins enable_reg|q*] \

-through [get_pins -hierarchical *|*ena*]] -end –hold

The target of the set_multicycle_path exception is limited to all fanouts of the register reg_en that feed the enable port of a register, which is done with the following option:

[get_fanouts [get_pins enable_reg|q*] -through [get_pins -hierarchical *|*ena*]]

Table 1 shows the new set-up and hold relationships of all enable-driven register-to-register paths in the design after the multicycle exceptions have been applied.

Table 1. Set-Up and Hold Relationships for Enable-Driven Registers

Source Register Destination Register Set-Up Relationship Hold Relationship
din_a[*]din_a_reg[*]2x (latch edge time)1x (latch edge time)
din_x[*]din_x_reg[*]2x (latch edge time)1x (latch edge time)
din_b[*]din_b_reg[*]2x (latch edge time)1x (latch edge time)
din_y[*]din_y_reg[*]2x (latch edge time)1x (latch edge time)
fast_mult:mult|*a_times_b[*]2x (latch edge time)1x (latch edge time)
fast_mult:mult|*x_times_y[*]2x (latch edge time)1x (latch edge time)
enable_regdin_a_reg[*],din_b_reg[*], a_times_b[*],x_times_y[*]2x (latch edge time)1x (latch edge time)

From Table 1, notice that the set-up and hold relationships that start at register enable_reg and end at any enable-driven register are 2 and 1, respectively. If these paths do not require the set-up and hold relationship to be modified, you can apply the following multicycle exceptions to apply the original relationships:

set_multicycle_path 1 -from [get_pins enable_reg|q*] –end -setup

set_multicycle_path 0 -from [get_pins enable_reg|q*] –end –hold

Download example circuit clock_enable_multicycle.qar.