Timing Analyzer create_generated_clock Command

The Timing Analyzer considers clock dividers, ripple clocks, or circuits that modify or change the characteristics of the incoming or master clock as generated clocks. You should define the output of these circuits as generated clocks. This definition allows the Timing Analyzer to analyze these clocks and account for any network latency associated with them.

You can use the create_generated_clock command to create generated clocks. The following list shows the create_generated_clock command and the available options:

create_generated_clock
   [-name <clock name>]
   -source <master pin>
   [-edges <edge list>]
   [-edge_shift <shift list>]
   [-divide_by <factor>]
   [-multiply_by <factor>]
   [-duty_cycle <percent>]
   [-add]
   [-invert]
   [-master_clock <clock>]
   [-phase <phase>]
   [-offset <offset>]
   <source objects>

Table 1 describes the options for the create_generated_clock command.

 

Table 1. Options Description for create_generated_clock Command

Option Description
-name <clock name> Name of the generated clock, for example, clk_x2. If you do not specify the clock name, the clock name is the same as the first node to which it is assigned.
-source <master pin> The <master pin> specifies the node in the design from which the clock settings derive.
-edges <edge list> |-edge_shift <shift list> The -edges option specifies the new rising and falling edges with respect to the master clock’s rising and falling edges. The master clock’s rising and falling edges are numbered 1..<n> starting with the first rising edge, for example, edge 1. The first falling edge after that is edge number 2, the next rising edge number 3, and so on. The <edge list> must be in increasing order. The same edge may be used for two entries to indicate a clock pulse independent of the original waveform’s duty cycle. edge_shift specifies the amount of shift for each edge in the <edge list>. The -invert option can be used to invert the clock after the -edges and -edge_shifts are applied. (1)
-divide_by <factor> | -multiply_by <factor> The divide_by and multiply_by factors are based on the first rising edge of the clock, and extend or contract the waveform by the specified factors. For example, a -divide_by 2 is equivalent to -edges {1 3 5}. For multiplied clocks, the duty cycle can also be specified. The Timing Analyzer supports specifying multiply and divide factors at the same time.
-duty_cycle <percent> Specifies the duty cycle of the generated clock. The duty cycle is applied last.
-add Allows you to specify more than one clock to the same pin.
-invert Inversion is applied at the output of the clock after all other modifications are applied, except duty cycle.
-master_clock <clock> master_clock is used to specify the clock if multiple clocks exist at the master pin.
-phase <phase> Specifies the phase of the generated clock.
-offset <offset> Specifies the offset of the generated clock.
<source objects> Specifies the port(s) or pin(s) to which the assignment applies.

Note:

  1. The Timing Analyzer supports a maximum of three edges in the edge list.

Source latencies are based on clock network delays from the master clock (not necessarily the master pin). You can use the set_clock_latency -source command to override the source latency.

Figure 1 shows waveforms for the following SDC commands that create an inverted generated clock based on a 10 ns clock.

create_clock -period 10 [get_ports clk]
create_generated_clock -divide_by 1 -invert -source [get_registers clk] \
    [get_registers gen|clkreg]
Figure 1. Generating an Inverted Clock

Figure 2 shows waveforms for the following SDC commands that modify the generated clock using the -edges and -edge_shift options.

create_clock -period 10 -waveform { 0 5 } [get_ports clk]
# Creates a divide-by-2 clock
create_generated_clock -source [get_ports clk] -edges { 1 3 5 } \
    [get_registers clkdivA|clkreg]
# Creates a divide-by-2 clock independent of the master clock's duty cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -edge_shift  0 5 0 } \
    [get_registers clkdivB|clkreg]
Figure 2. Edges & Edge Shifting a Generated Clock

Figure 3 shows wafeforms for the following SDC commands that demonstrate the effect of the -multiply option on the generated clock.

create_clock -period 10 -waveform { 0 5 } [get_ports clk]
# Creates a multiply-by-2 clock
create_generated_clock -source [get_ports clk] -multiply_by 2 \
    [get_registers clkmult|clkreg]
Figure 3. Multiplying a Generated Clock