There are two forms of clock latency: source and network. Source latency is the propagation delay from the origin of the clock to the clock definition point (for example, a clock port), and network latency is the propagation delay from a clock definition point to a register’s clock pin. The total latency (or clock propagation delay) at a register’s clock pin is the sum of the source and network latencies in the clock path.
You can use the set_clock_latency command to specify input delay constraints to ports in the design. The following list shows the set_clock_latency command including the available options:
set_clock_latency -source [-rise | -fall] [-late | -early] <delay> <object list>
Table 1 describes the options for the set_clock_latency command.