JEDEC Compliance

Altera is a member of the Joint Electron Device Engineering Council (JEDEC), and is an active participant and supporter of JC14, the JEDEC committee responsible for quality and reliability standards. Internal specifications are in compliance with all applicable JEDEC standards. Altera sells standard products to a broad customer base, and believes that JEDEC provides an excellent forum for manufacturers and customers from all market segments to discuss quality and reliability concerns and issues, and to formulate standard approaches.

JEDEC maintains an active web site, complete with a library of standards and publications for free download, at Two examples that provide an overview to some of the other reliability standards include:

JEP143, published November, 2001, (currently in balloting for revision), Solid State Reliability Assessment Qualification Methodologies. This publication is a reference for the suite of reliability, modeling, and qualification documents and publications that are available through JEDEC. It provides background on reliability assessment and qualification methodologies and includes a brief overview on each of the pertinent documents and publications.

JEP122-B, published August, 2003, Failure Mechanisms and Models for Silicon Semiconductor Devices. This publication provides a list of failure mechanisms, and their associated activation energies or acceleration factors, that may be used in making system failure rate estimations when the only available data is based on tests performed under accelerated stress test conditions. The Sum of the Failure Rates method is used.

Altera is also a participant in the following JEDEC committees:

  • JC11 (Package Outline Standardization)
  • JC15 (Electrical and Thermal Characterization Techniques for Electronic Packages and Interconnects)
  • JC42 (Solid State Memories)