| Intellectual Property (IP): Interfaces and Peripherals |
| Data Sheets |
| Motor Control IP Suite Components for Drive-on-Chip Reference Designs |
| Application Notes |
AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report  |
| AN 712: Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report |
AN 690: PCI Express DMA Reference Design for Stratix V Devices  |
| AN 710: Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report |
| AN704: FPGA-based Safety Separation Design Flow for Rapid IEC |
| AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller |
AN 696: Using the JESD204B MegaCore Function in Arria V Devices
Altera JESD204B MegaCore Function and ADI AD9250 Hardware Checkout Report (1 MB)
AN 696 Reference Design Example (3 MB) |
| AN669: Drive-On-Chip Reference Design |
AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
TSE Single Port Reference Design Arria II GX (4 MB)
TSE Single Port Reference Design Stratix IV GX (7 MB)
TSE Single Port RGMI Dev Arria II GX ACDS-12.0sp2 (733 KB)
TSE Single Port RGMII Starter Arria V GX ACDS-12.0sp2 (861 KB)
TSE Single Port SGMII Dev Stratix IV GX ACDS-12.0sp2 (702 KB)
TSE Single Port SGMII Dev Stratix VGX ACDS-12.0sp2 (1 MB)
TSE Single Port SGMII Starter Arria V GX ACDS-12.0sp2 (862 KB) |
AN 633: Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and GX Transceivers
TSE Loopback Reference Design ArriaII GX (7 MB)
TSE Loopback Reference Design Stratix IV (6 MB) |
AN617: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices
Design Files for AN 617 (2 MB) |
| AN599: Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design |
| AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Design |
AN585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN585: Test Cases (3 MB) |
| AN 569: SDI Flywheel Video Decoder Reference Design |
RapidIO Interoperability with TI 6488 DSP Reference Design
(AN568: RapidIO Interoperability with TI 6488 DSP Reference Design) |
| AN561: Stratix II GX 10GbE Loopback Reference Design |
| AN 541: SerialLite II Hardware Debugging Guide |
AN 532: An SOPC Builder PCI Express Design with GUI Interface
Design Files for AN 532 (5 MB) |
| AN 483: Triple Speed Ethernet Data Path Reference Design |
| AN 456: PCI Express High Performance Reference Design |
| AN 431: PCI Express to External Memory Reference Design |
AN 415: DDR and DDR2 SDRAM ECC Reference Design
ECC Reference Design Files (242 bytes) |
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
three controller example (26 KB)
two controller example (15 KB) |
| AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver |
| AN 320: OpenCore Plus Evaluation of Megafunctions |
| AN 49: Implementing CRCCs in Altera Devices |
AN 697: Implementing Audio IP in SDI II on Arria V Development Board
Design Files for AN 697 (3 MB) |
| Functional Specifications |
| FS 12: pci_mt32 MegaCore Function Reference Design |
| FS 10: pci_mt64 MegaCore Function Reference Design |
| User Guides |
| Stratix 10 Avalon-MM Interface for PCIe Solutions User Guide |
| Stratix 10 Avalon-ST Interface for PCIe Solutions User Guide |
| Arria 10 Avalon-ST Interface for PCIe Solutions User Guide |
| Hybrid Memory Cube Controller IP Core User Guide |
| Arria V Avalon-MM Interface for PCIe Solutions User Guide |
| Arria V Avalon-ST Interface for PCIe Solutions User Guide |
| Arria V Hard IP for PCI Express User Guide |
| Avalon Tri-State Conduit Components User Guide |
Avalon Verification IP Suite User Guide
(Includes Qsys tutorials for Verilog HDL and VHDL)
Avalon Verification IP Suite Design Files (46 KB) |
| Cyclone V Hard IP for PCI Express User Guide |
| DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Gui |
| DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide |
| IP Compiler for PCI Express User Guide |
JESD204B IP Core User Guide
Altera JESD204B RX Address Map and Register Definitions (465 KB)
Altera JESD204B TX Address Map and Register Definitions (356 KB) |
| Low Latency 100-Gbps Ethernet IP Core User Guide |
| Low Latency Ethernet 10G MAC User Guide |
| SDI II MegaCore Function User Guide |
| Serial Digital Interface (SDI) MegaCore Function User Guide |
| Stratix V Avalon-MM Interface for PCIe Solutions User Guide |
| Triple Speed Ethernet MegaCore Function User Guide |
| 100G Interlaken MegaCore Function User Guide |
| 10-Gbps Ethernet MAC MegaCore Function User Guide |
| 25-Gbps Ethernet IP Core User Guide |
| 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide |
| 50G Interlaken MegaCore Function User Guide |
| Altera Transceiver PHY IP Core User Guide |
| Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide |
| Arria 10 Avalon-MM Interface for PCIe Solutions User Guide |
| Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide |
| Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide |
| Arria V GZ Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface |
| Arria V GZ Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface v13.1 |
| Arria V GZ Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface with DMA |
| Arria V Hard IP for PCI Express User Guide, v13.1 |
| ASI MegaCore Function User Guide |
| Avalon Verification IP Suite v11.0 User Guide |
Avalon-MM 256-Bit Hard IP for PCI Express User Guide
(Avalon-MM 256-Bit Hard IP for PCI Express User Guide) |
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
user_led.zip (4 KB) |
| CPRI IP Core User Guide |
| CPRI v6.0 MegaCore Function User Guide |
| Cyclone V Avalon-MM Interface for PCIe Solutions User Guide |
| Cyclone V Avalon-ST Interface for PCIe Solutions User Guide |
| DDR and DDR2 SDRAM Controller Compiler User Guide |
| DDR Timing Wizard User Guide |
| HyperTransport MegaCore Function User Guide |
| Interlaken MegaCore Function User Guide |
| Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide |
| PCI Compiler User Guide |
| QDRII SRAM Controller MegaCore Function User Guide |
| RapidIO II MegaCore Function User Guide |
| RapidIO MegaCore Function User Guide |
| RLDRAM II Controller MegaCore Function User Guide |
| SerialLite III Streaming MegaCore Function User Guide |
| Stratix II GX Embedded Gigabit Ethernet MAC/PHY User's Guide |
| Stratix V Avalon-ST Interface for PCIe Solutions User Guide |
| Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide |
| V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide |
| White Papers |
| Automated Generation of Hardware Accelerators With Direct Memory Access From ANSI/ISO Standard C Functions |
| DDR & DDR2 SDRAM Controller Compiler FAQ |
| The Efficiency of the DDR & DDR2 SDRAM Controller Compiler |
| Upgrading a DDR SDRAM Controller MegaCore Function v2.1.* Design to v2.2.0 |
| Errata Sheets |
Altera IP Release Notes
(All IP and Nios II release notes are combined into one document) |
| PCI Express Compiler v2.1.1 Errata Sheet |